最近発表論文(セキュアスキャン設計関連)

  1. Hideo Fujiwara and Marie E. J. Obien,"Secure and Testable Scan Design Using Extended de Bruijn Graphs," 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp.413-418, Jan. 2010.[📄PDF | →acm.org][Slides]
  2. Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, and Hideo Tamamoto, "SREEP: Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design," 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2010), pp. 193-196, April 2010[📄PDF | →ieee.org]
  3. 藤原克哉、藤原秀雄、オビエンマリーエンジェリン, 玉本英夫、"セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成,"電子情報通信学会和文論文誌D-I, Vol. J93-D, No. 11, pp. 2426-2436, Nov. 2010.[📄PDF | →ieice.org]
  4. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "SREEP-2:  SR-Equivalent Generator for Secure and Testable Scan Design," 11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp. 7-12, Dec. 2010[📄PDF][Slides]
  5. Hideo Fujiwara, Katsuya Fujiwara, and Hideo Tamamoto, "Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack," 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.818-823, Jan. 2011.[📄PDF | →ieee.org][Slides]
  6. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design," IEICE Trans. on Inf. and Syst., Vol. E94-D, No. 7, pp. 1430-1439, July 2011.[📄PDF | →ieice.org]
  7. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "SR-Quasi-Equivalents: Yet Another Approach to Secure and Testable Scan Design," 12th IEEE Workshop on RTL and High Level Testing (WRTLT'11), pp. 77-82, Nov. 2011. [📄PDF][Slides]
  8. Katsuya Fujiwara and Hideo Fujiwara, "WAGSR: Web Application for Generalized Feed Forward Shift Registers," 13th IEEE Workshop on RTL and High Level Testing (WRTLT'12), pp.1.2.1-1.2.7, Nov. 2012.[📄PDF][Slides]
  9. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "Secure and Testable Scan Design Utilizing shift Register Quasi-Equivalents," IPSJ Trans. on System LSI Design Methodology, Vol. 6, pp. 27-33, Feb. 2013.[→jstage(PDF)]
  10. Katsuya Fujiwara and Hideo Fujiwara, "Generalized Feed Forward Shift Registers and their Application to Secure Scan Design," IEICE Trans. on Inf. and Syst., Vol. E96-D, No. 5, pp. 1125-1133, May 2013.[📄PDF | →ieice.org]
  11. Hideo Fujiwara and Katsuya Fujiwara, "Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers," IEICE Trans. on Inf. and Syst., Vol. E98-D, No. 10, pp. 1852-1855, Oct. 2015. [📄PDF→ieice.org]
  12. Hideo Fujiwara and Katsuya Fujiwara, “Properties of Generalized Feedback Shift Registers for Secure Scan Design,” IEICE Trans. on Inf. and Syst., Vol. E99-D, No. 4, pp. 1255-1258, Apr. 2016.[📄PDF→ieice.org]
  13. Hideo Fujiwara and Katsuya Fujiwara, “Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design,” IEICE Trans. on Inf. and Syst., Vol. E99-D, No. 8, pp. 2182-2185, Aug. 2016.[📄PDF→ieice.org]
  14. Hideo Fujiwara and Katsuya Fujiwara, “Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents,” IEICE Trans. on Inf. and Syst., Vol. E100-D, No.9, pp. - , Sep. 2017. (to appear) 

Citation Indexの高い論文

  1. Franc Brglez and Hideo Fujiwara, "A neutral netlist of 10 combinational circuits and a tageted translator in fortran," Special Session on ATPG and Fault Simulator", Proc. Int. Symp. on Circuits and Systems, pp. 663-698, 1985.  (Citation Index=1736 by Google Scholar) [📄Slides|→ISCAS85 Benchmarks]
  2. Hideo Fujiwara and Takeshi Shimono, "On the acceleration of test generation algorithms," IEEE Trans. on Computers, Vol. C-32, No. 12, pp. 1137-1144, Dec. 1983.  (Citation Index=818 by Google Scholar)[📄PDF|→ieee.org]
  3. Hideo Fujiwara, Logic Testing and Design for Testability, MIT Press, Sept. 1985. (Citation Index=546 by Google Scholar) [Slides|→MIT Press]
  4. Hideo Fujiwara and Shunichi Toida, "The complexity of fault detection problems for combinational logic circuits," IEEE Trans. on Computers, Vol. C-31, No. 6, pp.555-560, June 1982. (Citation Index=145 by Google Scholar)[📄PDF|→ieee.org]
  5. Hideo Fujiwara and Kozo Kinoshita, "A design of programmable logic arrays with universal tests," IEEE Trans. on Computers, Vol. C-30, No. 11, pp.823-828, Nov. 1981. (Citation Index=120 by Google Scholar)[📄PDF|→ieee.org (TC)|→ieee.org (TCAS)]
  6. Hideo Fujiwara, “FAN: A fanout-oriented test pattern generation algorithm," Proc. 1985 Int. Symp. Circuits and Systems, pp.671-674, June 1985. (Citation Index=78 by Google Scholar) [📄PDF]
  7. Hideo Fujiwara and Akihiro Yamamoto, "Parity-Scan Design to Reduce the Cost of Test Application," IEEE Trans. on Computer-Aided Design, Vol. 12, No. 10, pp. 1604-1611, October 1993. (Citation Index=69 by Google Scholar) [📄PDF] [→ieee.org]
  8. Hideo Fujiwara, "A new PLA design for universal testability," IEEE Trans. on Computers, Vol. C-33, No. 8, pp. 745-750, Aug. 1984. (Citation Index=64 by Google Scholar) [📄PDF][→ieee.org]
  9. Hideo Fujiwara and Kozo Kinoshita, "On the computational complexity of system diagnosis," IEEE Trans. on Computers, Vol. C-27, No.10, pp.881-885, Oct. 1978. (Citation Index=55 by Google Scholar) [📄PDF][→ieee.org]
  10. Hideo Fujiwara, "Computational complexity of controllability/observability problems for combinational circuits," IEEE Trans. on Comput., Vol. 39, No. 6, pp762-767, June 1990. (Citation Index=52 by Google Scholar)[📄PDF] [→ieee.org]
  11. Hideo Fujiwara, Yoichi Nagao, Tsutomu Sasao, and Kozo Kinoshita, "Easily testable sequential machines with extra inputs," IEEE Trans. on Computers, Vol. C-24, No. 8, pp. 821-826, Aug. 1975. (Citation Index=52 by Google Scholar)[📄PDF] [→ieee.org]
  12. Hideo Fujiwara, "A new class of sequential circuits with combinational test generation complexity," IEEE Trans. on Comput., Vol. 49, No. 9, pp. 895-905, September 2000. (Citation Index=45 by Google Scholar)[📄PDF][→ieee.org]

著書・編書
  1. 尾崎弘、藤原秀雄、論理数学の基礎、オーム社、昭和55年10月
  2. 樹下行三、藤原秀雄、ディジタル回路の故障診断(上)、工学図書、昭和58年1月
  3. Hideo Fujiwara, Logic Testing and Design for Testability, MIT Press, 昭和 60年9月  [Slides|→MIT Press]
  4. 藤原秀雄、コンピュータの設計とテスト、工学図書、平成2年8月
  5. 当麻喜弘、南谷崇、藤原秀雄、フォールトトレラントシステムの構成と設計、槙書店、平 成3年3月
  6. 藤原秀雄(分担執筆)、新版情報処理ハンドブック(情報処理学会(編))、オーム社、平成7年11月
  7. 藤原秀雄、コンピュータ設計概論、工学図書、平成10年10月
  8. 藤原秀雄(分担執筆)、エンサイクロペディア電子情報通信ハンドブック(電子情報通信学会(編))、オーム社、平成10年11月
  9. Hideo Fujiwara (編集委員長), 10th Anniversary Compendium of Papers from Asian Test Symposium, IEEE, July 2001.
  10. 藤原秀雄、ディジタルシステムの設計とテスト、工学図書、平成16年5月
  11. Hideo Fujiwara (編集委員長), V. Singh (副委員長), 20th Anniversary Compendium of Papers from Asian Test Symposium, IEEE, Sept. 2011.

解説・総説・コラム

  1. 藤原秀雄、回路診断技術の動向、電子通信学会誌、Vol.67, No.2, pp.211-213, 昭 和59年2月
  2. 藤原秀雄、テスト生成と故障シミュレーション、情報処理学会誌、Vol. 25, No.10, pp.1119-1124, 昭和59年10月
  3. Hideo Fujiwara, et al., Test research in Japan, IEEE Design and Test of Computers, Vol. 5, pp.60-79, Oct. 1988.
  4. 藤原秀雄、カスタムLSIのテスト技法、計測自動制御学会、計測と制御、Vol.28, No.10, pp.-876-881, 平成元年10月
  5. 藤原秀雄編、特集:VLSIのテスト容易化設計、情報処理、Vol.30, No.12, pp.1450-1493, 平成元年12月
  6. 藤原秀雄、テスト生成アルゴリズム、人工知能学会誌、Vol.8, No.3, pp.166-172, 平成5年3月[📄PDF]
  7. 藤原秀雄、VLSIのテスト、電子情報通信学会誌、Vol.77, No.3, pp.288-295, 平成6年3月
  8. 藤原秀雄、テスティング技術論文特集の発行にあたって、電子情報通信学会論文誌(DI), Vol. J79-D-I, No.12, pp. 1007-1008, December 1996
  9. Hideo Fujiwara, "Needed: Third-generation ATPG benchmarks," The Last Byte, IEEE Design & Test of Computers, Vol.15, No.1, p.96, January-March, 1998. [📄PDF]
  10. 井上美智子、藤原秀雄、テスト容易性を考慮したVLSI高位合成:サーベイと今後の動向、日本信頼性学会誌「信頼性」, Vol. 20, No.5, pp. 333-340, June 1998
  11. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, and Yervant Zorian, "ATS Roundtable: Design & Test Education in Asia," IEEE Design & Test of Computers, Vol. 21, No. 4, pp. 331-338, July-August 2004.[📄PDF]

学術雑誌論文

  1. 藤原秀雄、樹下行三、"シフトレジスタを持つ順序回路の故障検査系列の構成法、" 電子通 信学会論文誌(C)、Vol. 54C, No.2, pp.132-139、昭和46年2月[📄PDF]
  2. 藤原、樹下、"セル構造をした論理回路の故障診断、" 電子通 信学会論文誌(C)、Vol. 54C, No.5, pp.435-436、昭和46年5月[📄PDF]
  3. 藤原、樹下、”出力端子付加による診断容易な順序機械について、”電子通信 学会論文誌(D)、Vol. 55D, No.12, pp. 807-814、昭和47年12月[📄PDF]
  4. H.Fujiwara and K.Kinoshita, "Minimization of nondeterministic finite local automata," Technology Reports of the Osaka University, Vol. 22, No.1047, pp.227-233, 1972.[📄PDF]
  5. 藤原、樹下、”順序機械の出力可観測形実現と故障検査、”電子通信学会論文 誌(D)、Vol.56D, No.8, pp. 473-479、昭和48年8月[📄PDF]
  6. H.Fujiwara and K.Kinoshita, "Design of diagnosable sequential machines utilizing extra outputs," Technology Reports of the Osaka University, Vol. 23, No. 1140, pp. 541-550, Oct. 1973.[📄PDF]
  7. H.Fujiwara and K.Kinoshita, "Easily testable sequential machines," Technology Reports of the Osaka University, Vol. 24, No. 1214, pp. 653-663,1974.[📄PDF]
  8. H. Fujiwara and K. Kinoshita,"Design of diagnosable sequential machines utilizing extra outputs," IEEE Trans. on Computers, Vol. C-23, No.2, pp.138-145, Feb. 1974. [📄PDF[→ieee.org]
  9. 藤原、樹下、”不完全記述順序機械の故障検査、”電子通信学会論文誌(D)、 Vol.57D, No.10, pp. 527-533, 昭和49年10月[📄PDF]
  10. 藤原、樹下、”入力付加による故障検査容易な順序機械’、”電子通信学会論 文誌(D)、Vol.57D, No.10, pp.589-595, 昭和49年10月[📄PDF]
  11. 藤原、樹下、”初期状態識別系列を持たない不完全記述順序機械の故障検査、” 電子通信学会論文誌(D)、Vol.58D, No.6, pp.298-305, 昭和50年6月[📄PDF]
  12. H. Fujiwara, Y. Nagao, T. Sasao, and K. Kinoshita, "Easily testable sequential machines with extra inputs," IEEE Trans. on Computers, Vol. C-24, No. 8, pp. 821-826, Aug. 1975. [📄PDF [→ieee.org]
  13. 藤原、樹下、”ド・ブルインのグラフと故障検査容易な順序機械について、” 電子通信学会論文誌(D)、Vol.59D, No.5, pp.372-374, 昭和51年5月[📄PDF]
  14. 藤原、樹下、”故障検査容易な非同期順序機械について、”電子通信学会論 文誌(D)、Vol.59D, No.8, pp. 560-566, 昭和51年8月[📄PDF]
  15. 金、藤原、樹下、”確率的診断可能なシステムの構成について、”電子通信 学会論文誌(D)、Vol.60D,No.9, pp.750-757、昭和52年9月[📄PDF]
  16. H. Fujiwara and K.Kinoshita, "Checking experiments for stable memory faults in sequential machines," Journal of Design Automation and Fault Tolerant Computing, Vol.2, No.1, pp. 3-14, Jan. 1978.[📄PDF]
  17. H. Fujiwara and K. Kinoshita, "Connection assignments for probabilistically diagnosable systems," IEEE Trans. on Computers, Vol. C-27, No. 3, pp. 280-283 , March 1978. [📄PDF][→ieee.org]
  18. H. Fujiwara and K. Kinoshita, "Some existence theorem for probabilistically diagnosable systems," IEEE Trans. on Computers, Vol. C-27, No.4, pp.380-384, April 1978. [📄PDF][→ieee.org]
  19. 藤原、樹下、”検査データ圧縮のための検査機構について、”電子通信学会論 文誌(D)、Vol.61D, No.6, pp.427-433, 昭和53年6月[📄PDF]
  20. H. Fujiwara and K. Kinoshita, "On the computational complexity of system diagnosis," IEEE Trans. on Computers, Vol. C-27, No.10, pp.881-885, Oct. 1978. [📄PDF][→ieee.org]
  21. H.Fujiwara and K.Kinoshita,"Testing logic circuits with compressed data," Journal of Design Automation and Fault Tolerant Computing, Vol.3, No.4, pp. 211-225, 1979. [📄PDF]
  22. 藤原、尾崎、”自己検査を有するシステム診断モデル、”電子通信学会論文 誌(D)、Vol. 62D, No.10, pp. 625-632、昭和54年10月[📄PDF]
  23. 金、藤原、樹下、”自己診断システムにおける診断能力の改善法、”電子通 信学会論文誌(D)、Vol. 63D, No.1, pp. 93-100、昭和55年1月[📄PDF]
  24. 藤原、尾崎、”変数縮退に関して閉じた論理関数族と故障検査への応用、”電 子通信学会論文誌(D)、Vol. 63D, No.4, pp.279-286、昭和55年4月[📄PDF]
  25. H. Fujiwara, "On closedness and test complexity of logic circuits," IEEE Trans. on Computers, Vol. C-30, No.8, pp.556-562, Oct. 1981.  [📄PDF[→ieee.org]
  26. H. Fujiwara and K. Kinoshita, "A design of programmable logic arrays with universal tests," Joint Special Issue on Design for Testability, IEEE Trans. on Computers, Vol. C-30, No. 11, pp.823-828; and IEEE Trans. on Circuits and Systems, Vol. CAS-28, No. 11, pp. 1027-1032, Nov. 1981.  [📄PDF[→ieee.org (TC)] [📄PDF][→ieee.org (TCAS)]
  27. H. Fujiwara and S. Toida, "The complexity of fault detection problems for combinational circuits," IEEE Trans. on Computers, Vol. C-31, No. 6, pp.555-560, June 1982.  [📄PDF][→ieee.org]
  28. 藤原、下野、尾崎、”組合せ回路における分岐指向型検査入力生成法、”情 報処理学会論文誌、Vol. 24, No. 1, pp.1-8, 昭和58年1月 [📄PDF]
  29. 藤原、”PLA における検査容易化設計、”電子通信学会論文誌(D)、 Vol.66D, No.9, pp.1046-1053, 昭和58年9月 [📄PDF]
  30. K. Saluja, K. Kinoshita, and H.Fujiwara, "An easily testable design of programmable logic arrays for multiple faults," IEEE Trans. on Computers, Vol. C-32, No. 11, pp.1038-1046, Nov. 1983. [📄PDF][→ieee.org]
  31. H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. on Computers, Vol. C-32, No. 12, pp. 1137-1144, Dec. 1983.  [📄PDF][→ieee.org]
  32. A. Motohara and H. Fujiwara, "Design for testability for complete test coverage," IEEE Design and Test of Computers, Vol. 1, No. 4, pp.25-32 , Nov. 1984. [📄PDF][→ieee.org]
  33. H. Fujiwara, "A new PLA design for universal testability," IEEE Trans. on Computers, Vol. C-33, No. 8, pp. 745-750, Aug. 1984. [📄PDF[→ieee.org]
  34. H. Fujiwara, "Design for testability and built-in self test for VLSI circuits," Microprocessor and Microsystems, Vol.10, No.3, pp.139-147, April 1986. [📄PDF]
  35. R. Treuer, H. Fujiwara, and V.K. Agarwal, "Implementing a built-in self-test PLA design," IEEE Design and Test of Computers, Vol. 3, No. 2, pp.37-48, April 1986.  [📄PDF][→ieee.org]
  36. K. K. Saluja, H. Fujiwara, and K. Kinoshita, "A testable design of programmable logic arrays with universal control and minimal overhead," International Journal of Computers and Mathematics with Applications, vol.13, no.5/6, pp.503-517, Feb. 1987.[📄PDF]
  37. 藤原秀雄、"組合せ論理回路における故障検査問題の計算複雑度について、"情報処理 学会論文誌、Vol.27, no.8, pp.768-773, Aug. 1986. [📄PDF]
  38. 藤原秀雄、"ランダムテスト可能なPLAの一設計法、" 電子通信学会論文誌、 Vol.J69-D, No.12,pp.1862-1869, Dec. 1986. [📄PDF]
  39. R. Treuer, V.K.Agarwal, and H. Fujiwara, "A new built-in self-test design for PLA's with high fault coverage and low overhead," IEEE Trans. on Comput., Vol. C-36, No. 3, pp.369-373, March 1987. [📄PDF]
  40. H. Fujiwara, "A design of programmable logic arrays with random-pattern-testability," IEEE Trans. on Computer-Aided Design, Vol.7, No.1, pp.5-10, Jan. 1988. [📄PDF][→ieee.org]
  41. H. Fujiwara and A. Motohara, "Fast test pattern generation using a multiprocessor system," Trans.of IEICE, Vol.E71, No.4, pp.441-447, April 1988. [📄PDF]
  42. H.Fujiwara, "Enhancing random-pattern coverage of programmable logic arrays via masking technique," IEEE Trans. Computer-Aided Design, Vol. 8, No. 9, pp. 1022-1025, Sept. 1989. [📄PDF][→ieee.org]
  43. H. Fujiwara, "Computational complexity of controllability/observability problems for combinational circuits," IEEE Trans. on Comput., Vol. 39, No. 6, pp762-767, June 1990.  [📄PDF][→ieee.org]
  44. H.Fujiwara and T. Inoue, "Optimal Granularity of test generation in a distributed system," IEEE Trans. on Computer-Aided Design, Vol. 9, No.8, pp.885-892, Aug. 1990. [📄PDF][→ieee.org]
  45. H.Fujiwara, "Three-Valued Neural Networks for Test Generation," Int. J. Computer Aided VLSI Design, Vol. 3, No. 3, pp. 273-290, 1991.[📄PDF]
  46. Y.Min and H.Fujiwara, "Fault Detection Capability of an O(mn) Test Generation Algorithm for PLAs," IEICE Trans., Vol. E74, No. 10, pp.3506-3512, 1991. [📄PDF]
  47. 藤野貴之、藤原秀雄、”論理回路のテスト生成のための3値ニューラルネット ワークモデル、”情報処理学会論文誌、Vol. 33, No.4, pp. 570-579, Apr. 1992.[📄PDF]
  48. 藤野貴之、藤原秀雄、”探索状態被覆性に基づく探索空間削減の一手法、” 電子情報通信学会論文誌 D-I, Vol. J76-D-I, No.5, pp.218-227, May 1993.[📄PDF]
  49. H. Fujiwara and A. Yamamoto, "Parity-Scan Design to Reduce the Cost of Test Application," IEEE Trans. on Computer-Aided Design, Vol. 12, No. 10, pp. 1604-1611, October 1993. [📄PDF][→ieee.org]
  50. 井上智生、米澤友紀、藤原秀雄、”テスト生成における並列処理の最適なシ ステム構成について、”電子情報通信学会論文誌 D-I, Vol. J76-D-I, No. 11, pp. 604-612, November 1993. [📄PDF]
  51. T. Fujino and H.Fujiwara, "A search space pruning method for test pattern generation using search state dominance," J. of Circuits, Systems and Computers, Vol.3, No. 4, pp. 859-875, December 1993. [📄PDF]
  52. T.Inoue, T. Yonezawa, H. Fujiwara, "Optimal granularity of parallel test generation on the Client-Agent-Server model" Trans. of Information Processing Society of Japan (情報処理学会論文誌). Vol. 35, No. 8, pp.1614-1623, 1994. [📄PDF]
  53. A. Fujiwara, T. Masuzawa, and H. Fujiwara, "An optimal parallel algorithm for the Euclidean distance maps of 2-D binary images," Information Processing Letters 54, pp. 295-300, 1995. 
  54. H. Fujiwara and T. Inoue, "Optimal granularity and scheme of parallel test generation in a distributed system," IEEE Trans. on Parallel and Distributed Systems, Vol. 6, No.7, pp. 677-686, July 1995. [📄PDF][→ieee.org]
  55. 藤原暁宏,増澤利光,藤原秀雄、”濃淡のあるディジタル画像の連結成分を求める並列アルゴリズム、”電子情報通信学会論文誌(DI), Vol. J79-D-I, No.5, pp. 215-225, May 1996. [📄PDF]
  56. 吉田大輔,増澤利光,藤原秀雄、”自律移動ロボット群のための停止故障耐性のある分散型問題解法、”電子情報通信学会論文誌(DI), Vol. J79-D-I, No.6, pp. 320-330, June 1996. [📄PDF]
  57. A. Fujiwara, M. Inoue, T. Masuzawa and H. Fujiwara, "A simple parallel algorithm for the medial axis transform," IEICE Trans. Info. & Syst., Vol. E79-D, No. 8, pp. 1038-1045, Aug. 1996. [📄PDF]
  58. T. Inoue, H. Maeda and H. Fujiwara, "On the Effect of Scheduling in Test Generation," IEICE Trans. Info. & Syst., Vol. E79-D, No. 8, pp. 1190-1197, Aug. 1996. [📄PDF]
  59. T. Inoue, T. Fujii and H. Fujiwara,"Performance Analysis of Parallel Test Generation for Combinational Circuits," IEICE Trans. Info. & Syst., Vol. E79-D, No. 9, pp. 1257-1265, Sept. 1996. [📄PDF]
  60. 四浦 洋、井上智生、増澤利光、藤原秀雄、”部分スキャンによる同期化可能な有限状態機械の合成について、”電子情報通信学会論文誌(DI), Vol. J79-D-I, No.12, pp. 1046-1054, December 1996. [📄PDF]
  61. 高畠勝之、井上美智子、増澤利光、藤原秀雄、”スルー演算を用いた非スキャン方式によるデータパスのテスト容易化設計、”電子情報通信学会論文誌(DI), Vol. J79-D-I, No.12, pp. 1063-1071, December 1996. [📄PDF]
  62. 道西博行、横平徳美、岡本卓爾、井上智生、藤原秀雄、”テーブル参照型FPGAにおける論理ブロックの検査、”電子情報通信学会論文誌(DI), Vol. J79-D-I, No.12, pp. 1141-1150, December 1996. [📄PDF]
  63. 藤原秀雄、大竹 哲史、高崎 智也、”組合せテスト生成複雑度でテスト生成可能な順序回路構造とその応用、”電子情報通信学会論文誌(DI), Vol. J80-D-I, No.2, pp. 155-163, February 1997. [📄PDF]  <電子情報通信学会  平成13年度情報・システムソサイエティ論文賞>[→ieice]
  64. 大竹 哲史、井上智生、藤原秀雄”回路疑似変換による順序回路テスト生成の一手法、”情報処理学会誌、Vol. 38, No. 5, pp. 1040-1049, May 1997. [📄PDF]
  65. T. Inoue S. Miyazaki, and H. Fujiwara, "Universal fault diagnosis for Look-up table FPGAs", IEEE Design & Test of Computers, Vol. 15, No. 1, pp. 39-44, January-March, 1998. [📄PDF][→ieee.org]
  66. 高崎智也、井上智生、藤原秀雄”内部平衡構造に基づく部分スキャン設計法に関する考察、”電子情報通信学会論文誌(DI)、Vol. J81-D-I, No. 3, pp. 318-327, March 1998. [📄PDF]
  67. M. Inoue, K. Noda, T. Higashimura, T. Masuzawa and H. Fujiwara, "High-Level Synthesis for Weakly Testable Data Paths", IEICE Trans. Inf. & Syst., Vol. E81-D, No. 7, pp. 645-653, July 1998. [📄PDF]
  68. 大竹哲史, 増澤利光, 藤原秀雄, "完全故障検出効率を保証するコントローラの非スキャンテスト容易化設計法", 電子情報通信学会論文誌 (DI), Vol. J81-D-I, No. 12, pp. 1259-1270, December 1998. [📄PDF<電子情報通信学会  平成13年度情報・システムソサイエティ論文賞>[→ieice]
  69. M. Inoue and H. Fujiwara, "An Approach to Test Synthesis from Higher Level", INTEGRATION, the VLSI journal, 26, pp. 101-116, 1998. [📄PDF]
  70. A. Fujiwara, M. Inoue, T. Masuzawa, and H. Fujiwara, "A cost optimal parallel algorithm for weighted distance transforms," Parallel computing, Vol.25, No.4, pp.405-416, 1999.
  71. 東村剛嗣, 井上美智子, 藤原秀雄, "弱可検査性のための設計目標抽出を利用したデータパス高位合成", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 2, pp. 401-409, Feb. 1999. [📄PDF]
  72. 大堀力, 井上美智子, 増澤利光, 藤原秀雄, "分散移動システムのための前後関係保存放送プロトコル", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 2, pp. 425-435, Feb. 1999. [📄PDF]
  73. 石水 隆,藤原 暁宏,井上 美智子,増澤 利光,藤原 秀雄, "選択問題を解くBSPモデル及びBSP*モデル上の並列アルゴリズム", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 4, pp.533-542, April 1999. [📄PDF]
  74. 林 邦彦,井上 美智子,増澤 利光,藤原 秀雄, "直交順序を保存する矩形の非交差配置問題", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 6, pp. 679-690, June 1999. [📄PDF]
  75. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue and H. Fujiwara, "Testing for the Programming Circuits of SRAM-Based FPGAs", IEICE Trans. Inf. & Syst., Vol. E82-D, No. 6, pp. 1051-1057, June 1999. [📄PDF]
  76. 和田 弘樹,増澤 利光,K.K.Saluja, 藤原 秀雄, "完全故障検出効率を保証するデータパスの非スキャンテスト容易化設計法", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 7, pp. 843-851, July 1999. [📄PDF<電子情報通信学会  平成13年度情報・システムソサイエティ論文賞>[→ieice]
  77. 細川利典、井上智生、平岡敏洋, 藤原 秀雄, "時間展開モデルを用いた無閉路順序回路のテスト系列圧縮方法", 電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 7, pp. 869-878, July 1999. [📄PDF]
  78. 守屋宣、井上美智子、増澤利光、藤原 秀雄, "共有メモリマルチプロセッサシステムにおける同期時間最適な無待機時計合せプロトコル", 電子情報通信学会論文誌 (DI), Vol. J83-D-I, No. 1, pp. 99-109, Jan. 2000. [📄PDF]
  79. 高崎智也、井上智生, 藤原 秀雄, "無閉路部分スキャン設計に基づくデータパスのテスト容易化高位合成", 電子情報通信学会論文誌 (DI), Vol. J83-D-I, No. 2, pp. 282-292, Feb. 2000. [📄PDF]
  80. T.Ishimizu, A.Fujiwara, M.Inoue, T.Masuzawa and H.Fujiwara, "Parallel algorithms for the all nearest neighbors of binary image on the BSP model," IEICE Transactions on Information and Systems, Vol. E83-D, No. 2, pp. 151-158, Feb. 2000. [📄PDF]
  81. S. Moriya, K. Suda, M. Inoue, T. Masuzawa and H. Fujiwara, "Wait-Free Linearizable Distributed Shared Memory", IEICE Trans. on Information and Systems, Vol. E83-D, No. 8, pp. 1611-1621, Aug. 2000. [📄PDF]
  82. 佐野ちいほ、三原隆宏、井上智生、Debesh K. Das, 藤原秀雄, "ホールド機能を考慮した順序回路の部分スキャン設計法" 電子情報通信学会論文誌(DI), Vol. J83-D-I, No. 9, pp. 981-990, Sept. 2000. [📄PDF]
  83. H. Fujiwara, "A new class of sequential circuits with combinational test generation complexity," IEEE Trans. on Comput., Vol. 49, No. 9, pp. 895-905, September 2000.  [📄PDF][→ieee.org]
  84. S. Ohtake, T. Masuzawa and H. Fujiwara, "A non-scan approach to DFT for Controllers Achieving 100% Fault Efficiency," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 5, pp. 553-566, Oct. 2000. [📄PDF][→JETTA]
  85. X. Li, P.Y.S.Cheung and H. Fujiwara, "LFSR-based deterministic TPG for two-pattern testing," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 5, pp. 419-426, Oct. 2000. [📄PDF][→JETTA]
  86. H.Matsui, M.Inoue, T.Masuzawa, and H.Fujiwara, "Fault-Tolerant and Self-Stabilizing Protocols using an Unreliable Failure Detector," IEICE Transactions on Information and Systems, Vol. E83-D, No. 10, pp. 1831-1840, Oct. 2000.[📄PDF]
  87. 浮穴学慈, 長谷川学, 片山喜章, 増澤利光, 藤原秀雄, "木ネットワーク上のヒープ順序構成自己安定プロトコル" 電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 1, pp. 48-57, Jan. 2001. [📄PDF]
  88. 井筒稔, 和田弘樹, 増澤利光, 藤原秀雄, "レジスタ転送レベルデータパスの単一制御可検査性に基づく組込み自己テスト容易化設計法," 電子情報通信学会論文誌(DI), Vol.J84-D-I, No.1, pp. 69-77, Jan. 2001. [📄PDF]
  89. 谷口博人, 井上美智子, 増澤利光, 藤原秀雄, "アドホックネットワークにおけるクラスタ構成法," 電子情報通信学会論文誌 D-1, Vol.J84-D-I, No.2, pp. 127-135, Feb. 2001. [📄PDF]
  90. 永井慎太郎, 和田弘樹, 大竹哲史, 藤原秀雄, "固定制御可検査性に基づくRTL回路の非スキャンテスト容易化設計法," 電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 5, pp. 454-465, May 2001. [📄PDF<電子情報通信学会  平成13年度情報・システムソサイエティ論文賞>[→ieice]
  91. 和田弘樹, 増澤利光, 藤原秀雄, "演算器の強可検査性を保証するテスト容易化高位合成," 電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 5, pp. 466-473, May 2001. [📄PDF]
  92. M. Inoue, E. Gizdarski, and H. Fujiwara,"Sequential circuits with combinational test generation complexity under single-fault assumption," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, No. 1, pp. 55-62, February 2002.  [📄PDF][→JETTA]
  93. 米田友和, 藤原秀雄, "連続可検査性に基づくコアベース・システムオンチップのテスト容易化設計法," 電子情報通信学会論文誌(DI), Vol. J85-D-I, No. 2, pp.173-183, Feb. 2002. [📄PDF]
  94. 永井慎太郎, 大竹哲史, 藤原秀雄, "レジスタ転送レベルでのデータフロー依存型回路の階層テスト容易化設計法," 情報処理学会論文誌、Vol. 43, No. 5, pp. 1278-1289, May 2002. [📄PDF]
  95. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,"Design for hierarchical two-pattern testability of data paths," IEICE Trans. on Information and Systems, Vol. E85-D, No. 6, pp. 975-984, June 2002. [📄PDF]
  96. 山口賢一, 和田弘樹, 増澤利光, 藤原秀雄, "レジスタ転送レベルデータパスの単一制御並行可検査性に基づく組込み自己テスト法," 電子情報通信学会論文誌(DI), Vol. J85-D-I, No.6, pp. 527-537, June 2002. [📄PDF]
  97. Yoshiaki Katayama, Eiichiro Ueda, Hideo Fujiwara, Toshimitsu Masuzawa, "A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings," Journal of Parallel and Distributed Computing, 62, pp. 865-884, 2002.
  98. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores," Journal of Electronic Testing: Theory and Applications (JETTA) Special Issue on Plug-and-Play Test Automation for System-on-a-Chip, Vol. 18, No. 4/5, pp. 487-501, Aug./Oct. 2002. [📄PDF][→JETTA]
  99. Dong Xiang and Hideo Fujiwara, "Handling the Pin Overhead Problem of DFTs for High Quality and At-Speed Test," IEEE Trans. on Computer Aided Design for Integrated Circuits and Systems, Vol. 21, No. 9, pp. 1105-1113, Sept. 2002. [📄PDF] [→ieee.org]
  100. 浮穴学慈, 片山喜章, 増澤利光, 藤原秀雄, "非停止永久故障に耐性を有する自己安定生成木構成プロトコル," 電子情報通信学会論文誌(DI)、電子情報通信学会論文誌(DI), Vol. J85-D-I, No.11, pp. 1007-1014, Nov. 2002. [📄PDF]
  101. Emil Gizdarski and Hideo Fujiwara, "SPIRIT: A Highly Robust Combinational Test Generation Algorithm," IEEE Trans. on Computer Aided Design for Integrated Circuits and Systems, Vol. 21, No. 12, pp. 1446-1458, Dec. 2002.  [📄PDF][→ieee.org]
  102. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara, "A Non-Scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency," IPSJ(Information Processing Society of Japan) Journal, Vol. 44, No. 5, pp. 1266-1275, May 2003. [📄PDF]
  103. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for two-pattern testability of controller-data path circuits," IEICE Trans. on Information and Systems, IEICE Trans. Inf.&Syst., Vol. E86-D, No.6, pp. 1042-1049, June 2003. [📄PDF]
  104. 山口 賢一, 井上 美智子, 藤原 秀雄, "階層BIST:低いハードウェアオーバヘッドを実現するTest-per-clcok方式BIST," 電子情報通信学会論文誌(DI), Vol. J86-D-I, No.7, pp. 467-479, July 2003. [📄PDF]
  105. Dong Xiang, Yi Xu, and Hideo Fujiwara, "Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution," IEEE Trans. on Computers,Vol. 52, No. 8, pp. 1063-1075, August 2003. [📄PDF] [→ieee.org]
  106. 神野 元彰, 井上 美智子, 藤原 秀雄, "ホールドとスイッチの機能を考慮した内部平衡構造," 電子情報通信学会論文誌(DI), Vol.J86-D-I, No.9, pp. 682-690, Sept. 2003. [📄PDF]
  107. 三輪 俊二郎, 大竹 哲史, 藤原 秀雄, "組合せテスト生成複雑度でパス遅延故障テスト生成可能な順序回路のクラス," 電子情報通信学会論文誌(DI), Vol. J86-D-I, No.11, pp. 809-820, November 2003. [📄PDF]
  108. Dong Xiang, Shan Gu, Hideo Fujiwara, "Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis," IEICE Transactions on Information and Systems, , Vol. E86-D, No. 11, pp.2407-2417 , Nov. 2003. [📄PDF]
  109. 岩垣 剛, 大竹 哲史, 藤原 秀雄, "不連続再収斂順序回路のパス遅延故障に対するテスト生成法," 電子情報通信学会論文誌(DI), Vol. J86-D-I, No.12, pp.872-883, December 2003. [📄PDF]
  110. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka and Hideo Fujiwara, "A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint," IEICE Trans. on Information and Systems, Vol. E86-D, No. 12, pp.2674-2683, Dec. 2003. [📄PDF]
  111. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka and Hideo Fujiwara, "A DFT Selection Method fo rReducing Test Application Time of System-on-Chips," IEICE Transactions on Information and Systems, Vol. E87-D, No.3, pp. 609-619, March 2004. [📄PDF]
  112. Erik Larsson and Hideo Fujiwara, "Preemptive System-on-Chip Test Scheduling," IEICE Transactions on Information and Systems, Vol. E87-D, No.3, pp. 620-629, March 2004. [📄PDF]
  113. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng, "Efficient Test Solutions for Core-based Designs," IEEE Trans. on CAD, Vol. 23, No. 5, pp. 758-775, May 2004. [📄PDF][→ieee.org]
  114. Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara, "New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency," Journal of Electronic Testing: Theory and Applications, Vol. 20, No. 3, pp. 315-323, June 2004. [📄PDF][→JETTA]
  115. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian, "Design & Test Education in Asia," IEEE Design and Test of Computers, vol..21,. no..4,. pp. 331-338,. Jul/Aug,. 2004. [📄PDF][→ieee.org]
  116. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A Design Scheme for Delay Testing of Controllers Using StateTransition Information," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms), Vol. E87-A, No. 12, pp.3200-3207, Dec. 2004. [📄PDF]
  117. 米田友和, 藤原 秀雄, "レジスタ転送レベル回路に対する連続透明化設計法," 電子情報通信学会論文誌(DI), Vol. J87-D-I, No.12, pp. 1110-1118, Dec. 2004. [📄PDF]
  118. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Delay Fault Testing of Processor Cores in Functional Mode," IEICE Transactions on Information and Systems, Vol. E88-D, No. 3, pp. 610-618, March 2005. [📄PDF] 
  119. Dong Xiang, Ming-jing Chen, Jia-guang Sun, and Hideo Fujiwara, "Improving Test Effectiveness of Scan-Based BIST by Scan Chain Partitioning," IEEE Trans. on CAD, Vol. 24, No. 6, pp. 916-927 , June 2005.  [📄PDF][→ieee.org]
  120. 井上美智子、神戸和子、Virendra Singh、藤原秀雄 "縮退故障とパス遅延故障のためのプロセッサの命令レベル自己テスト法," 電子情報通信学会和文論文誌D-I(LSIのテスト・検証・診断技術特集号, 招待論文), Vol. J88-D-I, No.6, pp. 1003-1011, June 2005. [📄PDF]
  121. 大谷浩平、大竹哲史、藤原秀雄 "縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対するテスト生成法," 電子情報通信学会和文論文誌D-I(LSIのテスト・検証・診断技術特集号), Vol. J88-D-I, No.6, pp. 1057-1064, June 2005. [📄PDF]
  122. Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara, "Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST," IEICE Transactions on Information and Systems, Vol. E88-D, No. 6, pp. 1210-1216, June 2005. [📄PDF]
  123. Zhiqiang You, Ken'ichi Yamaguchi, Michiko Inoue, Jacob Savir and Hideo Fujiwara, "Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths," IEICE Transactions on Information and Systems, Vol. E88-D, No. 8, pp. 1940-1947, Aug. 2005. [📄PDF]
  124. Chia Yee Ooi, Thomas Clouqueur, and Hideo Fujiwara, "Classification of Sequential Circuits based on tau^k Notation and Its Applications," IEICE Transactions on Information and Systems, Vol. E88-D, No. 12, pp.2738-2747, December 2005. [📄PDF]
  125. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, and Hideo Fujiwara,"Error identification in at-speed scan BIST environment in the presence of circuit and tester speed mismatch,"IEICE Transactions on Information and Systems, Vol. E89-D, No. 3, pp. 1165-1172, March 2006. [📄PDF]
  126. Masahide Miyazaki, Tomokazu Yoneda, and Hideo Fujiwara, "A Memory Grouping Method for reducing Memory BIST Logic of System-on-Chips," IEICE Transactions on Information and Systems, Vol. E89-D, No. 4, pp.1490-1497, April 2006. [📄PDF]
  127. Erik Larsson and Hideo Fujiwara,"System-on-Chip Test Scheduling with Reconfigurable Core Wrappers," IEEE Trans. on Very Large Scale Integration (VLSI)Systems, Vol. 14, No. 3, pp. 305-309, March 2006. [📄PDF][→ieee.org]
  128. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, and Hideo Fujiwara,"A Low Power Deterministic Test Using Scan Chain Disable Technique," "IEICE Transactions on Information and Systems, Vol. E89-D, No. 6, pp.1931-1939, June 2006. [📄PDF]
  129. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara "Non-Scan Design for Single-Port-Change Delay Fault Testability," IPSJ(Information Processing Society of Japan) Journal (Special Issue on Design Methodology of System LSIs), Vol. 47, No. 6, pp. 1619-1628, June 2006. [📄PDF]
  130. 岩田浩幸、米田友和、大竹哲史、藤原秀雄 "完全故障検出効率を保証するRTLデータパスの部分強可検査性に基づくテスト容易化設計法," 電子情報通信学会和文論文誌D-I(ディペンダブルコンピューティング特集号), Vol. J89-D, No.8, pp.1643-1653, Aug. 2006. [📄PDF]
  131. Yoshiyuki Nakamura, Jacob Savir, and Hideo Fujiwara,"Effect of BIST Pretest on IC Defect Level,"IEICE Transactions on Information and Systems, Vol.E89-D No.10 pp.2626-2636, Oct. 2006. [📄PDF]
  132. Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara,"Instruction-Based Self-Testing of Delay Faults in Pipelined Processors," IEEE Trans. on Very Large Scale Integration (VLSI)Systems, Vol. 14, No. 11, pp. 1203-1215, Nov. 2006. [📄PDF][→ieee.org]
  133. Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja and Hideo Fujiwara, "Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability," The IEICE Transactions on Information and Systems, Vol. E90-D, No. 1, pp.296-305, Jan. 2007. [📄PDF]
  134. Dong Xiang, Kaiwei Li, Jiaguang Sun, and Hideo Fujiwara, "Reconfigured Scan Forest for Test Application Cost, Test Data Volume and Test Power Reduction," IEEE Trans. on Computers, Vol. 56, No. 4, pp. 557-562, April 2007.  [📄PDF][→ieee.org]
  135. Dong Xiang, Kaiwei Ki, Hideo Fujiwara, Krishnaiyan Thulasiraman, and Jiaguang Sun, "Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture," IEEE Trans. on Circuits and Systems, Vol. 54, No. 5, pp. 450-454, May 2007. [📄PDF][→ieee.org]
  136. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, and Hideo Fujiwara, "Diagnosing At-speed Scan BIST Circuits Using a Low Speed and Low Memory Tester," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 7, pp. 790-800, July 2007. [📄PDF][→ieee.org]
  137. Chia Yee Ooi, Thomas Clouqueur, and Hideo Fujiwara,"Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation," IEICE Transactions on Information and Systems, Vol. E90-D, No. 8, pp.1202-1212, August 2007. [📄PDF]
  138. Dong Xiang, Mingjing Chen, and Hideo Fujiwara, "Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST," IEEE Trans. on Computers, Vol. 56, No. 12, pp. 1619-1628, December 2007. [📄PDF][→ieee.org]
  139. Ilia Polian and Hideo Fujiwara, "Functional Constraints vs. Test Compression in Scan-Based Delay Testing," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 23, No. 5, pp. 445-455, October 2007. [📄PDF][→JETTA]
  140. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, and Hideo Fujiwara, "Scheduling Power-Constrained Tests through the SoC Functional Bus," IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.736-746, March 2008. [📄PDF]
  141. Tomokazu Yoneda, Kimihiko Masuda, and Hideo Fujiwara, "Test Scheduling for Multi-Clock Domain SoCs under Power Constraint," IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.747-755, March 2008.[📄PDF] 
  142. Masato Nakazato, Michiko Inoue, Satoshi Ohtake, and Hideo Fujiwara, "Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors," IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.763-770, March 2008. [📄PDF]
  143. Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, and Hideo Fujiwara, "Effective Domain Partitioning for IP Core Wrapper Design Under Power Constraints," IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.807-814, March 2008. [📄PDF]
  144. Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, and Hideo Fujiwara, "A Reconfigurable Scan Architecture with Weighted Scan-Enable Signals for Deterministic BIST," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 6, pp.999-1012, June 2008. [📄PDF][→ieee.org]
  145. Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara, "On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time," IEICE Transactions on Information and Systems, Vol. E91-D, No. 7, pp.1999-2007, 2008. [📄PDF]
  146. Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara, "NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints," IEICE Transactions on Information and Systems, Vol. E91-D, No. 7, pp.2008-2017, 2008. [📄PDF]
  147. Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, and Chia Yee Ooi, "A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 9, pp. 1535-1544, Sept. 2008. [📄PDF][→ieee.org]
  148. Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, and Hideo Fujiwara, "Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips," IEICE Transactions on Information and Systems, Vol. E91-D, No. 10, pp.2440-2448, Oct. 2008. [📄PDF]
  149. 岡伸也, ChiaYee Ooi, 市原英行, 井上智生, 藤原秀雄 "部分スルー可検査性に基づく順序回路のテスト生成法," 電子情報通信学会和文論文誌D-I, Vol.J92-D,No.12,pp.2207-2216, Dec. 2009. [📄PDF]
  150. Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara, "A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint," IEICE Transactions on Information and Systems (Special Section on Test, Diagnosis and Verification of SOCs), Vol. E93-D, No. 1, pp. 24-32, January 2010. [📄PDF]
  151. Hongxia Fang, Krishnendu Chakrabarty, and Hideo Fujiwara, "RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences," Journal of Electronic Testing: Theory and Applications(JETTA), Volume 26, Issue 2, pp. 151-164, April 2010. [📄PDF][→JETTA]
  152. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara, "Design and Optimization of Transparency-Based TAM  for SoC Test," IEICE Trans. on Inf. and Syst., Vol.E93-D, No.6, pp. 1549-1559, June 2010. [📄PDF]
  153. Hiroshi Iwata, Satoshi Ohtake, and Hideo Fujiwara, "A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification," IEICE Transactions on Information and Systems, Vol. E93-D, No. 7, pp. 1857-1865, July 2010. [📄PDF]
  154. Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri, and Hideo Fujiwara, "A New Class of Easily Testable Assignment Decision Diagram," Malaysian Journal Computer Science (MJCS), Vol. 23, No. 1, pp. 1-17, 2010. [📄PDF]
  155. 藤原克哉、藤原秀雄、オビエンマリーエンジェリン, 玉本英夫、"セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成,"電子情報通信学会和文論文誌D-I, Vol. J93-D, No. 11, pp.2426-2436, Nov. 2010. [📄PDF]
  156. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Taavi Viilukas, and Hideo Fujiwara, "An Approach for Verification Assertions Reuse in RTL Test Pattern Generation," Journal of Shanghai Normal University, Vol. 39, No. 5, pp. 441-447, Oct. 2010. [📄PDF]
  157. Marie Engelene Jimenez Obien, Satoshi Ohtake, and Hideo Fujiwara, "F-Scan: A DFT Method for Functional Scan at RTL," IEICE Trans. on Inf. and Syst., Vol. E94-D, No. 1, pp. 104-113, Jan. 2011. [📄PDF]
  158. Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, and Hideo Fujiwara,"Balanced Secure Scan: Partial Scan Approach for Secrete Information Protection," Journal of Electronic Testing: Theory and Applications (JETTA), Vol.27, No.2, pp. 99-108, April 2011. [📄PDF][→JETTA]
  159. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design," IEICE Trans. on Inf. and Syst., Vol. E94-D, No. 7, pp. 1430-1439, July 2011. [📄PDF ]
  160. Chia Yee Ooi and Hideo Fujiwara, "A New Design-for-Testability Method based on Thru-Testability,"  Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, Issue 5, pp. 583-598, Oct. 2011. [📄PDF] [→JETTA]
  161. Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, and Hideo Fujiwara,"Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, No. 4 pp. 511-521, 2012. [📄PDF] [→JETTA]
  162. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, and Hideo Fujiwara, "A Failure Prediction Strategy for Transistor Aging," IEEE Trans. on Very Large Scale Integration Systems, Vol. 20, No. 11, pp. 1951-1959, Nov. 2012. [📄PDF][→ieee.org]
  163. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, and Hideo Fujiwara, "Test Pattern Ordering and Selection for High Quality Test Set under Constraints," IEICE Trans. on Inf. and Syst., Vol. E95-D, No. 12, pp.3001-3009, Dec. 2012. [📄PDF]
  164. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "Secure and Testable Scan Design Utilizing shift Register Quasi-Equivalents," IPSJ Trans. on System LSI Design Methodology, Vol. 6, pp. 27-33, Feb. 2013. [📄PDF]
  165. Katsuya Fujiwara and Hideo Fujiwara, "Generalized Feed Forward Shift Registers and their Application to Secure Scan Design," IEICE Trans. on Inf. and Syst., Vol. E96-D, No. 5, pp. 1125-1133, May 2013. [📄PDF→ieice.org]
  166. Debesh K. Das and Hideo Fujiwara, "One More Class of Sequential Circuits having Combinational Test Generation Complexity," Journal of Electronic Testing: Theory and Applications (JETTA), Vol.31, No.3, pp. 321-327, June 2015.  [📄PDF[→JETTA]
  167. Hideo Fujiwara and Katsuya Fujiwara, "Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers," IEICE Trans. on Inf. and Syst., Vol. E98-D, No. 10, pp. 1852-1855, Oct. 2015. [📄PDF→ieice.org]
  168. Hideo Fujiwara and Katsuya Fujiwara, “Properties of Generalized Feedback Shift Registers for Secure Scan Design,” IEICE Trans. on Inf. and Syst., Vol. E99-D, No. 4, pp. 1255-1258, Apr. 2016. [📄PDF→ieice.org]
  169. Hideo Fujiwara and Katsuya Fujiwara, “Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design,” IEICE Trans. on Inf. and Syst., Vol. E99-D, No. 8, pp. 2182-2185, Aug. 2016.[📄PDF→ieice.org]
  170. Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara, "Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip," IEEE Trans. on Computers, Vol. 65, No. 9, pp. 2767-2779, Sept. 2016.[📄PDF|→ieee.org]
  171. Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha’ameria, Hideo Fujiwara, “Test Register Insertion at RTL Based on Reduced BIST,”  Jurnal Teknologi (Sciences & Engineering), Vol. 79, No. 1, pp. 81 88, Jan. 2017. [📄PDF|→Journal Teknologi]

  172. Hideo Fujiwara and Katsuya Fujiwara, “Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents,” IEICE Trans. on Inf. and Syst., Vol. E100-D, No.9, pp. - , Sep. 2017. (to appear) 

国際会議論文
  1. Hideo Fujiwara and Kozo Kinoshita,"Testing logic circuits with compressed data," Proc. 8th IEEE Int. Symp. on Fault Tolerant Computing, pp. 108-113, June 1978.  [📄PDF]
  2. Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, and Kozo Kinoshita, "LORES - Logic Reorganization System," Proc. 15th Design Automation Conference, pp. 250-260, June 1978. [📄PDF]
  3. Hideo Fujiwara and Hiroshi Ozaki, "On the diagnosability of systems with self-testing units," Proc. 9th IEEE Int. Symp. on Fault Tolerant Computing, pp.157-160, June 1979.[📄PDF]
  4. Hideo Fujiwara, Kozo Kinoshita and Hiroshi Ozaki, "Universal test sets for programmable logic arrays," Proc. 10th IEEE Int. Symp. on Fault Tolerant Computing, pp.137-142, Oct. 1980.[📄PDF]
  5. Kewal K. Saluja, Kozo Kinoshita and Hideo Fujiwara, "A multiple fault testable design of programmable logic arrays," Proc. 11th IEEE Int. Symp. on Fault Tolerant Computing, pp.44-46, June 1981.[📄PDF]
  6. Hideo Fujiwara and Shunichi Toida, "The complexity of fault detection: An approach to design for testability," Proc. 12th IEEE Int. Symp. on Fault Tolerant Computing, pp.101-108, June 1982.[📄PDF]
  7. Hideo Fujiwara and Takeshi Shimono, "On the acceleration of test generation algorithms," Proc. 13th IEEE Int. Symp. on Fault Tolerant Computing, pp.98-105, 1983.[📄PDF]
  8. T. Ogihara, S. Murai, Y. Takamatsu, K. Kinoshita, and H. Fujiwara, "Test generation for scan design circuits with tri-state modules and bidirectional terminals," Proc. 20th Design Automation Conference, pp. 71-78, 1983.
  9. Hideo Fujiwara, "FAN: A fanout-oriented test pattern generation algorithm," Proc. 1985 IEEE Int. Symp. Circuits and Systems, pp.671-674, June 1985.[📄PDF]
  10. Franc Brglez and Hideo Fujiwara,  "A neutral netlist of 10 combinational circuits and a targeted translator in fortran," Special Session on ATPG and Fault Simulator, Proc. 1985 IEEE Int. Symp. on Circuits and Systems, pp. 663-698  June 1985. [📄Slides|→ISCAS85 Benchmarks]
  11. Robert Treuer, Hideo Fujiwara, and Vinod K. Agarwal, "An implementation of a new built-in self-test PLA design, " Proc. IEEE Int. Symp. on Circuit and Systems, pp.1301-1304, June 1985.[📄PDF]
  12. Robert Treuer, Hideo Fujiwara, and Vinod K. Agarwal, "A low overhead, high coverage, built-in self-test PLA design," Proc. 15th IEEE Int. Symp. on Fault-Tolerant Computing, pp.112-117, June 1985. [📄PDF]
  13. Kewal K. Saluja, Hideo Fujiwara, and Kozo Kinoshita, "A testable design of programmable logic arrays with universal control and minimal overhead," Proc. IEEE Int. Test Conf., pp.574-582, Nov. 1985. [📄PDF]
  14. Akira Motohara, Kenji Nishimura, Hideo Fujiwara, and Isao Shirakawa, "A parallel scheme for test-pattern generation," Proc. IEEE Fourth Int. Conf. on Computer-Aided Design, pp.156-159, Nov. 1986. [📄PDF]
  15. Hideo Fujiwara, "Design for high-speed testability," Proc. IEEE Int. Test Conf., pp.1132-1133,1987.  [📄PDF]
  16. Hideo Fujiwara, "Computational complexity of controllability/observability problems for combinational circuits," Proc. IEEE Int. Symp. on Fault-Tolerant Computing, pp. 64 - 69 , June 1988. [📄PDF]
  17. Hideo Fujiwara, Osamu Fujisawa, and Kazunori Hikone,"Enhancing random-pattern coverage of programmable logic arrays via masking technique," Proc. IEEE Int. Test Conf., pp.642 -648 , Sept. 1988. [📄PDF]
  18. Hideo Fujiwara and Tomoo Inoue, "Analysis of parallel processing for test generation in a distributed system," Proc. of Joint Symposium on Fault-Tolerant Computing, pp.128- 133, in China, July 1989. [📄PDF]
  19. Hideo Fujiwara and Tomoo Inoue, "Optimal Granularity of test generation in a distributed system," Proc. IEEE Int. Conf. on Computer-Aided Design, pp.158-161, Nov. 1989. [📄PDF]
  20. Hideo Fujiwara, "Three-valued neural networks for test generation," Proc. 20th IEEE Int. Symp. on Fault Tolerant Computing, pp.64-71, 1990. [📄PDF]
  21. Takayuki Fujino and Hideo Fujiwara, "An efficient test generation algorithm based on search state dominance," Proc. 22nd IEEE Int. Symp. on Fault Tolerant Computing, pp.246-253, July 1992.[📄PDF]
  22. Hideo Fujiwara and Akihiro Yamamoto, "Parity-scan design to reduce the cost of test application," Proc. IEEE Int. Test Conf., pp.283-292, Sept. 1992.[📄PDF]
  23. Tomoo Inoue, Tomonori Yonezawa and Hideo Fujiwara, "An Optimal Scheme of Parallel Processing for Test Generation in a Distributed System," Proc. 2nd IEEE Asian Test Symposium, pp. 8-13, November 1993.
  24. Tomoo Inoue, Takaharu Fujii and Hideo Fujiwara, "On the performance analysis of parallel processing for test generation," Proc. 3rd IEEE Asian Test Symposium, pp. 69-74, November 1994.
  25. Tomoo Inoue, Hironori Maeda and Hideo Fujiwara, "A scheduling problem in test generation," Proc. 1995 IEEE VLSI Test Symposium, pp. 344-349, May 1995.[📄PDF]
  26. Akihiro Fujiwara, Toshimitsu Masuzawa and Hideo Fujiwara, "An optimal parallel algorithm for the Euclidean distance maps of binary images," Proc. IEEE First ICAAAPP, p.928, April 1995.
  27. Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira and Takuji Okamoto, "Universal test complexity of field-programmable gate arrays," Proc. 1995 IEEE Asian Test Symposium, pp.259-265, November 1995. [📄PDF]
  28. Yasurou Satou, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara. "A Snapshot Algorithm for Distributed Mobile Systems", Proceedings of the 16th International Conference on Distributed Computing Systems, pp. 734-743, May 1996.
  29. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A simple parallel algorithm for the medeal axis transform of binary images," Proc Second IEEE International Conference on Algorithms and Architectures for Parallel Processing, pp.1-8, June 1996
  30. Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue and Hideo Fujiwara, "A test methodology for interconnect structures of LUT-based FPGAs," Proc. 1996 IEEE Asian Test Symposium, pp. 68-74, November 1996.
  31. Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra and Hideo Fujiwara, "An approach to the synthesis of synchronizable finite state machines with partial scan," Proc. 1996 IEEE Asian Test Symposium, pp. 130-135, November 1996.  [📄PDF]
  32. Katuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Non-scan design for testable data paths using thru operation," Proc. Asia and South Pacific Design Automation Conference, pp. 313-318, Jan. 1997.
  33. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A parallel algorithm for weighted distance transforms", Proc. 11th International Parallel Processing Symposium, pp. 407-412, Apr, 1997.
  34. Eiichiou Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa and Hideo Fujiwara, "A latency-optimal superstabilizing mutual exclusion protocol", Proc. 3rd Workshop on self-stabilizing systems, pp. 110-124, Aug, 1997.
  35. Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa and Hideo Fujiwara, "Optimal wait-free clock synchronization protocol on a shared-memory multi-processor system," Proc. Workshop on Distributed Algorithms, pp. 290-304, September 1997.
  36. Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "Sequential test generation based on circuit pseudo-transformation," Proc. 1997 IEEE Asian Test Symposium, pp. 62-67, November 1997.[📄PDF]
  37. Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue and Hideo Fujiwara, "Testing for the programming circuit of LUT-based FPGAs," Proc. 1997 IEEE Asian Test Symposium, pp. 242-247, November 1997. [📄PDF]
  38. Tomoo Inoue, Satoshi Miyazaki and Hideo Fujiwara, "On the complexity of universal fault diagnosis for look-up table FPGAs," Proc. 1997 IEEE Asian Test Symposium, pp. 276-281, November 1997. [📄PDF]
  39. Tomoya Takasaki, Tomoo Inoue and Hideo Fujiwara, "Partial scan design methods based on internally balanced structure," Proc. Asia and South Pacific Design Automation Conference, pp. 211-216, Feb. 1998.
  40. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A layout adjustment algorithm for disjoint rectangles preserving orthogonal order," Proc. 6th International Symposium on Graph Drawing (Lecture notes in computer science 1547), pp. 183-197, Aug. 1998.
  41. Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method for controllers to achieve complete fault efficiency", IEEE the 7th asian test symposium (ATS'98), pp. 204-211, Dec. 1998.[📄PDF]
  42. Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa and Hideo Fujiwara, "A High-Level Synthesis Method for Weakly Testable Data Paths", IEEE the 7th asian test symposium (ATS'98), pp. 40-45, Dec. 1998.[📄PDF]
  43. Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara and Hideo Fujiwara, "An Optimal Time Expansion Model Based on Combinational ATPG for RT Level Circuits", IEEE the 7th asian test symposium (ATS'98), pp. 190-197, Dec. 1998.[📄PDF]
  44. Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, and Hideo Fujiwara, "Self-stabilizing wait-free clock synchronization with bounded space", Proceedings of the 2nd International Conference on Principles of Distributed Systems, pp.183-197, Dec. 1998.
  45. Hiroki Wada, Toshimitsu Masuzawa, Kewal K.Saluja, and Hideo Fujiwara,"A DFT method for RTL data paths achieving 100% fault efficiency under hierachical test environment,'' Proceedings of IEEE European Test Workshop, May 1999.[📄PDF]
  46. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, and Hideo Fujiwara, "Parallel algorithms for finding all nearest neighbors of binary images on the BSP model,'' Proceedings of Joint Symposium on Parallel Processing, pp.253-260, June 1999.
  47. Akihiro Fujiwara, Takashi Ishimizu, Michiko Inoue, Toshimitsu Masuzawa, and Hideo Fujiwara, "Parallel selection algorithms for CGM and BSP with application to sorting,'' Proceedings of Joint Symposium on Parallel Processing, pp.261-268, June 1999.
  48. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, and Hideo Fujiwara, "Parallel algorithms for all nearest neighbors of binary images on the BSP model,'' Proceedings of 1999 International Symposium on Parallel Architectures, Algorithms, and Networks, pp.394-399, June 1999.
  49. T. Takasaki, T. Inoue and H. Fujiwara, "A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure", IEEE the 8th Asian Test Symposium (ATS'99), pp. 309-314, Nov. 1999. [📄PDF]
  50. Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description", IEEE the 8th Asian Test Symposium (ATS'99), pp. 5-12, Nov. 1999.[📄PDF]
  51. Debesh Kumar Das, Satoshi Ohtake and Hideo Fujiwara, "New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency", IEEE the 8th Asian Test Symposium (ATS'99), pp. 263-268, Nov. 1999.[📄PDF]
  52. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka and Hideo Fujiwara, "Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model", IEEE the 8th Asian Test Symposium (ATS'99), pp. 192-199, Nov. 1999. [📄PDF]
  53. Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja and Hideo Fujiwara, "Design for strong testability of RTL data paths to provide complete fault efficiency," Proc. of 13th International Conf. on VLSI Design, pp. 300-305, Jan. 2000.[📄PDF]
  54. Hideo Fujiwara, "A new definition and a new class of sequential circuits with combinational test generation complexity," Proc. of 13th International Conference on VLSI Design, pp. 288-293, Jan. 2000.[📄PDF]
  55. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method at register-transfer level to achieve complete fault efficiency," Proc. of Asia and South Pacific Design Automation 2000 (ASP-DAC 2000), pp. 599-604, Jan. 2000.[📄PDF]
  56. Emil Gizdarski and Hideo Fujiwara, "A new data structure for SAT-based static learning with impact on test generation," Digest of IEEE European Test Workshop (ETW 2000), pp. 313-314, May 2000.[📄PDF]
  57. Tomoo Inoue, Debesh K. Das, Takahiro Mihara, Chiiho Sano and Hideo Fujiwara, "Test generation and design-for-testability based on acyclic structure with hold registers," Digest of IEEE 2000 Int. Workshop on RTL ATPG & DFT (WRTLT2000), pp. 1-10, Sept. 2000. [📄PDF]
  58. Toshimitsu Masuzawa, Minoru Izutsu, Hiroshi Wada, and Hideo Fujiwara, "A DFT method for single-control testability of RTL data paths for BIST," Digest of IEEE 2000 Int. Workshop on RTL ATPG & DFT (WRTLT2000), pp. 52-60, Sept. 2000.
  59. Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara, "A non-scan DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency," Digest of IEEE 2000 Int. Workshop on RTL ATPG & DFT (WRTLT2000), pp. 61-77, Sept. 2000.[📄PDF]
  60. Dong Xiang, Y. Xu, and Hideo Fujiwara, "Non-scan design for testability for synchronous sequential circuits based on conflict analysis",Proc. Int. Test Conf., pp. 520-529, Oct. 2000.[📄PDF]
  61. Tomoo Inoue, Debesh K. Das, Takahiro Mihara, Chiho Sano, and Hideo Fujiwara, "Test generation for acyclic sequential circuits with hold registers",Proc. ICCAD, pp. 550-556, Nov. 2000.[📄PDF]
  62. Michiko Inoue, Emil Gizdarski, and Hideo Fujiwara, "A class of sequential circuits with combinational test generation complexity under single-fault assumption", IEEE the 9th Asian Test Symposium (ATS 2000), pp. 398-403, Dec. 2000.[📄PDF]
  63. Toshimitsu Masuzawa, Minoru Izutsu, Hiroshi Wada, and Hideo Fujiwara, "Single-control testability of RTL data paths for BIST", IEEE the 9th Asian Test Symposium (ATS 2000), pp. 210-215, Dec. 2000.[📄PDF]
  64. Emil Gizdarski and Hideo Fujiwara, "SPIRIT: Satisfiability problem implementation for redundancy identification and test generation", IEEE the 9th Asian Test Symposium (ATS 2000), pp. 171-178, Dec. 2000.[📄PDF]
  65. Xiaowei Li, Toshimitsu Masuzawa, and Hideo Fujiwara, "Strong self-testability for data paths high-level synthesis", IEEE the 9th Asian Test Symposium (ATS 2000), pp. 229-234, Dec. 2000. [📄PDF]
  66. Debesh K. Das, B. B. Bhattacharya, Satoshi Ohtake, and Hideo Fujiwara, "Testable Design of Sequential Circuits with Improved Fault Efficiency", Proc. 14th International Conference on VLSI Design, pp. 128-133, January 3-7, 2001.[📄PDF]
  67. Satoshi Ohtake, Shintaro Nagai, Hiroshi Wada and Hideo Fujiwara, "A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability," Asia and South Pacific Design Automation Conference 2001(ASP-DAC2001), pp. 331-334, Feb. 2001.[📄PDF]
  68. Emil Gizdarski and Hideo Fujiwara, "SPIRIT: A Highly Robust Combinational Test Generation Algorithm", Proc. 19th IEEE VLSI Test Symposium, Los Angeles, CA, USA, pp. 346-351, April 29 - May 3, 2001 .[📄PDF]
  69. Emil Gizdarski and Hideo Fujiwara, "A Framework on Low Complexity Static Learning", Proc. 38th Design Automation Conference, Las Vegas Convention Center, pp. 546-549, June 18-22, 2001.[📄PDF]
  70. Tomokazu Yoneda and Hideo Fujiwara, "A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability," IEEE the 10th Asian Test Symposium (ATS 2001), pp. 193-198, Nov. 2001.[📄PDF]
  71. Kenichi Yamaguchi, Hiroshi Wada, Toshimitsu Masuzawa, and Hideo Fujiwara, "A BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths," IEEE the 10th Asian Test Symposium (ATS 2001), pp. 313-318, Nov. 2001. [📄PDF]
  72. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for Hierarchical Two-Pattern Testability of Data Paths," IEEE the 10th Asian Test Symposium (ATS 2001), pp. 11-16, Nov. 2001.[📄PDF]
  73. Tomoo Inoue, T. Miura, A. Tamura, and Hideo Fujiwara, "A Scheduling Method in High-Level Synthesis for RTL Acyclic Partial Scan Design," Digest of Papers, IEEE 2001 Workshop on RTL ATPG & DFT, pp. 7-12, Nov. 2001. [📄PDF]
  74. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Testability of Systems-on-a-Chip with Built-In Self Testable Cores," Digest of Papers, IEEE 2001 Workshop on RTL ATPG & DFT, pp. 28-37, Nov. 2001.[📄PDF]
  75. Shintaro Nagai, Satoshi Ohtake, and Hideo Fujiwara, "A Design for Hierarchical Testability for RTL Data Paths," Digest of Papers, IEEE 2001 Workshop on RTL ATPG & DFT, pp. 128-133, Nov. 2001. [📄PDF]
  76. Satoshi Ohtake, Shunjiro Miwa, and Hideo Fujiwara, "A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits," Proceedings of 20th IEEE VLSI Test Symposium, pp. 321-327, May 2002.[📄PDF]
  77. Emil Gizdarski and Hideo Fujiwara, "Fault Set Partition for Efficient Width Compression," Digest of 7th IEEE European Test Workshop, pp. 13-14, May 2002.[📄PDF]
  78. Erik Larsson and Hideo Fujiwara, "Power Constrained Preemptive TAM Scheduling," Digest of 7th IEEE European Test Workshop, pp. 411- 416, May 2002.[📄PDF]
  79. Michiko Inoue, Chikateru Jinno, and Hideo Fujiwara, "An Extended Class of Sequential Circuits with Combinational Test Generation Complexity," Proc. of 20th International Conference on Computer Design, pp. 200-205, Sept. 16 -18, 2002.[📄PDF]
  80. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for Two-Pattern Testability of Controller-Data Path Circuits," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 73-79, Nov. 2002.[📄PDF]
  81. Dong Xiang, Shan Gu, and Hideo Fujiwara, "Non-Scan Design for Testability based on Fault-oriented Conflict Analysis," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 86-91, Nov. 2002. [📄PDF]
  82. Tomoo Inoue, Tomokazu Miura, Akio Tamura, and Hideo Fujiwara, "A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 128-133, Nov. 2002. [📄PDF]
  83. Emil Gizdarski and Hideo Fujiwara, "Fault Set Partition for Efficient Width Compression," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 194-199, Nov. 2002. [📄PDF]
  84. Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng, "Integrated Test Scheduling, Test Parallelization and TAM Design," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 397-404, Nov. 2002.  <IEEE ATS'02 Best Paper Award> [📄PDF]
  85. Erik Larsson and Hideo Fujiwara, "Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers," Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02) , pp. 6-11, Nov. 2002.
  86. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Transparency of RTL Circuits," Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02) , pp. 18-23, Nov. 2002. [📄PDF]
  87. Kenichi Yamaguchi, Michiko Inoue, and Hideo Fujiwara, "Hierarchical BIST: Test-per-clock BIST with low overhead," Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02) , pp. 42-47, Nov. 2002.
  88. Tomoo Inoue and Hideo Fujiwara, "A Partial Scan Design with Orthogonal Scan Paths," Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02) , pp. 38-41, Nov. 2002.
  89. Satoshi Ohtake, Kouhei Ohtani and Hideo Fujiwara, "A method of test generation for path delay faults using stuck-at fault test generation algorithms," Proc. Design Automation and Test in Europe 2003 (DATE03) , pp. 310-315, March 2003. [📄PDF]
  90. Erik Larsson, and Hideo Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs," Proc. 21st IEEE VLSI Test Symposium (VTS'03), pp. 319-324, April-May 2003. [📄PDF]
  91. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Transparency of Cores in System-on-a-Chip," Proc. 21st IEEE VLSI Test Symposium (VTS'03), pp.287-292, April-May 2003. [📄PDF]
  92. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A Path Delay Test Generation Method for Sequential Circuits Based on Reducibility to Combinational Test Generation," Dig. of Papers, 8th IEEE European Test Workshop, pp.307-312, May 2003. [📄PDF]
  93. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara, "Test Synthesis for Datapaths using Datapath-Controller Functions," Dig. of Papers, 8th IEEE European Test Workshop, pp.207-208, May 2003. [📄PDF]
  94. Tomokazu Yoneda, Tetsuo Uchiyama and Hideo Fujiwara, "Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability," IEEE International Test Conference 2003 (ITC'03), pp.415-422, Sep. 2003. [📄PDF]
  95. Erik Larsson and Hideo Fujiwara, "Optimal System-on-Chip Test Scheduling," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.306-311, Nov. 2003.[📄PDF]
  96. Dong Xiang, M-J. Chen, J-G. Sun, and Hideo Fujiwara, "Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.12-17, Nov. 2003. [📄PDF]
  97. Dong Xiang, S. Gu, and Hideo Fujiwara, "Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controllers via Conflict Analysis," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.300-303, Nov. 2003. [📄PDF]
  98. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, and Hideo Fujiwara, "A DFT Selection Method for Reducing Test Application Time of System-on-Chips," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.412-417, Nov. 2003. [📄PDF]
  99. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, and Hideo Fujiwara, "A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.130-135, Nov. 2003. [📄PDF]
  100. Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara,"Software-Based Delay Fault Testing of Processor Cores," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.68-71, Nov. 2003. [📄PDF]
  101. Michiko Inoue, K. Suzuki, H. Okamoto, and Hideo Fujiwara, "Test Synthesis for Datapaths using Datapath-Controller Functions," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.294-299, Nov. 2003. [📄PDF]
  102. Tsuyoshi Iwagaki, Satoshi Ohtake, and Hideo Fujiwara, "Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models," Proc. of IEEE the 12th Asian Test Symposium (ATS'03), pp.58-63, Nov. 2003. [📄PDF]
  103. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "An Approach to Non-Scan Design for Delay Fault Testability of Controllers ," Digest of Papers IEEE the 4th Workshop on RTL and High Level Testing (WRTLT '03), pp.79-85, Nov. 2003.  <IEEE WRTLT'03 Best Paper Award> [📄PDF]
  104. Hao Wu, Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "Test Length Minimization under Power Constraints for Combinational Circuits," IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.125-127, Nov. 2003. [📄PDF]
  105. Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "On the non-scan BIST schemes under power constraints for RTL data paths," IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.14-21, Nov. 2003. [📄PDF]
  106. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Instruction-Based Delay Fault Self-Testing of Processor Cores," Proc. International Conference on VLSI Design 2004, pp. 933-938, Jan. 2004. [📄PDF]
  107. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A Design Methodology to Realize Delay Testable Controllers Using State Transition Information, " Proc. 9th IEEE European Test Symposium (ETS'04) , pp. 168-173, May 2004. [📄PDF]
  108. Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara and Patrick Girard, "An Efficient Scan Tree Design for Test Time Reduction," Proc. 9th IEEE European Test Symposium (ETS'04) , pp. 174-179, May 2004. [📄PDF]
  109. Samiha Mourad and Hideo Fujiwara, "Design for Reliability," Proc. Instrumentation and Measurement Technology Conference (IMTC 2004), May 2004. [📄PDF]
  110. Yusuke Saga, Tomokazu Yoneda, Hideo Fujiwara, "Serial and Parallel TAM Designs for System-on-Chip Interconnects Based on 2-Pattern Testability," IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp. 13-18, Nov. 2004.  [📄PDF]
  111. Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara, "Defect Level vs. Yield and Fault Coverage in the Presence of an Imperfect BIST," IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp. 79-84, Nov. 2004.  [📄PDF]
  112. Michiko Inoue, Kazuko Kambe, Naotaka Hoashi, Hideo Fujiwara, "Instruction-Based Self-Test for Sequential Modules in Processors," IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp. 109-114, Nov. 2004. [📄PDF]
  113. Zhiqiang You, Kenichi Yamaguchi, Michiko Inoue, Jacob Savir, and Hideo Fujiwara,"Power-Constrained Test Scheduling for RTL Datapaths of Non-scan BIST Schemes," Proc. IEEE 13th Asian Test Symposium (ATS'04), pp. 32-39, Nov. 2004. [📄PDF]
  114. Kazuko Kambe, Michiko Inoue, and Hideo Fujiwara, "Efficient Template Generation for Instruction-Based Self-Test of Processor Cores," Proc. IEEE 13th Asian Test Symposium (ATS'04), pp. 152-157, Nov. 2004.   [📄PDF]
  115. Chia Yee Ooi and Hideo Fujiwara, "Classification of Sequential Circuits Based on tau**k Notation," Proc. IEEE 13th Asian Test Symposium (ATS'04), pp. 348-353, Nov. 2004. [📄PDF]
  116. Debesh K. Das, Tomoo Inoue, Susanta Chakraborty, and Hideo Fujiwara, "Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity," Proc. IEEE 13th Asian Test Symposium (ATS'04), pp. 342-247, Nov. 2004.  [📄PDF]
  117. Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard, "Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture," 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05) , pp. 19-26, April 2005. [📄PDF]
  118. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell, "Electrical Behavior of GOS Faults in Domino Logic," 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05) , pp. 210-215, April 2005.  [📄PDF]
  119. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell, "Electrical analysis of a domino logic cell with GOS faults," IEEE Workshop on Current & Defect Based Testing, pp. 34-41, 2005. [📄PDF]
  120. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Program-Based Testing of Super-scalar Microprocessors," IEEE North Atlantic Test Workshop 2005, pp.79-86, May 2005. [📄PDF]
  121. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Instruction-Based Delay Fault Self-Testing of Pipelined Processor Cores," 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) , pp.5686-5689, May 2005. [📄PDF]
  122. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-at Test Generation," 10th IEEE European Test Symposium (ETS '05) , pp. 48-53, May 22-25, 2005. [📄PDF]
  123. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara, "Perfect Error Identification in At-Speed BIST Environment," IEEE 6th Workshop on RTL and High Level Testing, pp.1-11, July 2005. [📄PDF]
  124. Dong Xiang, Kai-wei Li, Hideo Fujiwara, "Localizing Test Power Consumption for Scan Testing," IEEE 6th Workshop on RTL and High Level Testing, pp. 18-23, July 2005.
  125. Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara,"Matrices of Multiple Weights for Test Response Compaction with Unknown Values," IEEE 6th Workshop on RTL and High Level Testing, pp. 24-30, July 2005. [📄PDF]
  126. Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara, "A Memory Grouping Method for reducing Memory BIST Logic of System-on-Chips," IEEE 6th Workshop on RTL and High Level Testing, pp. 31-37, July 2005. [📄PDF]
  127. Masato Nakazato, Satoshi Ohtake, K.K. Saluja, and Hideo Fujiwara, "Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability," IEEE 6th Workshop on RTL and High Level Testing, pp. 50-60, July 2005.  <IEEE WRTLT'05 Best Paper Award>  [📄PDF]
  128. Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara, "Test Generation Complexity for Path Delay Faults Based on tau^k-Notation," IEEE 6th Workshop on RTL and High Level Testing, pp. 61-72, July 2005.
  129. Toshinori Hosokawa, Hideo Fujiwara, "A Functional Test Method for State Observable FSMs," IEEE 6th Workshop on RTL and High Level Testing, pp. 123-130, July 2005. [📄PDF]
  130. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara, "A Low Power Deterministic Test Using Scan Chain Disable Technique," IEEE 6th Workshop on RTL and High Level Testing, pp. 184-191, July 2005.  [📄PDF]
  131. Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara, "Design and Analysis of Multiple Weight Linear Compactors of Responses Containing Unknown Values," IEEE International Test Conference 2005, pp. 1099-1108, Nov. 2005. [📄PDF]
  132. Ilia Polian and Hideo Fujiwara, "Functional Constraints vs. Test Compression in Scan-Based Delay Testing," 2nd IEEE International GHz/Gbps Test Workshop (GTW 2005), pp. 91-100, Nov. 2005. [📄PDF]
  133. Tomokazu Yoneda, Hisakazu Takakuwa, and Hideo Fujiwara, "Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability," IEEE the 14th Asian Test Symposium (ATS'05), pp. 150-155, Dec. 2005. [📄PDF]
  134. Thomas Clouqueur, Kewal K. Saluja, and Hideo Fujiwara, "A Class of Linear Space Compactors for Enhanced Diagnosis," IEEE the 14th Asian Test Symposium (ATS'05), pp. 260-265, Dec. 2005. [📄PDF]
  135. Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, and Hideo Fujiwara, "A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency," IEEE the 14th Asian Test Symposium (ATS'05), pp. 306-311, Dec. 2005. [📄PDF]
  136. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara, "Design for Testability Based on Single-Port-Change Delay Testing for Data Paths," IEEE the 14th Asian Test Symposium (ATS'05), pp. 254-259, Dec. 2005. [📄PDF]
  137. Kazuko Kambe, Tsuyoshi Iwagaki, Michiko Inoue, and Hideo Fujiwara, "Efficient Constraint Extraction for Template-Based Processor Self-Test Generation," IEEE the 14th Asian Test Symposium (ATS'05), pp. 444-447, Dec. 2005. [📄PDF]
  138. Hideyuki Ichihara, Naoki Okamoto, Tomoo Inoue, Toshinori Hosokawa, and Hideo Fujiwara, "An Effective Design for Hierarchical Test Generation Based on Strong Testability," IEEE the 14th Asian Test Symposium (ATS'05), pp. 288-293, Dec. 2005. [📄PDF]
  139. Dong Xiang, Ming-Jing Chen, and Hideo Fujiwara, "Using Weighted Test Signals to Improve the Effectiveness of Scan-Based BIST," IEEE the 14th Asian Test Symposium (ATS'05), pp. 126-131, Dec. 2005. [📄PDF]
  140. Dong Xiang, Kai-Wei Li, and Hideo Fujiwara, "Design for Cost-Effective Scan Testing By Reconfiguring Scan Flip-Flops," IEEE the 14th Asian Test Symposium (ATS'05), pp. 318-321, Dec. 2005. [📄PDF]
  141. Masahide Miyazaki, Tomokazu Yoneda and Hideo Fujiwara, "A Memory Grouping Method for Sharing Memory BIST Logic," 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), pp. 671-676, Jan. 2006. [📄PDF]
  142. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara and Michel Renovell, "Electrical Behavior of GOS Fault affected Domino Logic Cell," Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006), pp. 183-189, Jan. 2006.  <IEEE DELTA'06 Best Paper Award> [📄PDF]
  143. Ilia Polian and Hideo Fujiwara, "Functional Constraints vs. Test Compression in Scan-Based Delay Testing," Proc. Design, Automation and Test in Europe 2006 (DATE'06) , pp. 1039-1044, March 2006. [📄PDF]
  144. Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara, "Power-Constrained Test Scheduling for Multi-Clock Domain SoCs," Proc. Design, Automation and Test in Europe 2006 (DATE'06) , pp. 297-302, March 2006. [📄PDF]
  145. Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara, "BIST Pretest of ICs: Risks and Benefits," IEEE 24th VLSI Test Symposium (VTS'06), pp. 142-147, May 2006. [📄PDF]
  146. Yuki Yoshikawa, Satoshi Ohtake, and Hideo Fujiwara, "An Approach to Reduce Over-testing of Path Delay Faults in Data Paths Using RT-level Information," Digest of Papers, 11th IEEE European Test Symposium, pp. 146-151, May 2006. [📄PDF]
  147. Zhiqiang You, Michiko Inoue, and Hideo Fujiwara, "Extended Compatibilities for Scan Tree Construction," Digest of Papers, 11th IEEE European Test Symposium, pp. 13-18, May 2006. [📄PDF]
  148. Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, and Hideo Fujiwara, "Diagnosis in Designs with Block Compactors," Digest of Papers, 11th IEEE European Test Symposium, pp. 199-204, May 2006.  [📄PDF]
  149. Chia Yee Ooi and Hideo Fujiwara, "A New Class of Sequential Circuits with Acyclic Test Generation Complexity," 24th IEEE International Conference on Computer Design (ICCD'06), pp. 425-431, October 2006. [📄PDF]
  150. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara, "Power-Constrained SOC Test Schedules through Utilization of Functional Buses," 24th IEEE International Conference on Computer Design (ICCD'06), pp. 230-236, October 2006. [📄PDF]
  151. Dong Xiang, Kaiwei Li, Hideo Fujiwara and Jiaguang Sun, "Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests," 24th IEEE International Conference on Computer Design (ICCD'06), pp. 446-451, October 2006. [📄PDF]
  152. Tsuyoshi Iwagaki, Satoshi Ohtake, and Hideo Fujiwara,"A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits," IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp. 308-313, October 2006. [📄PDF]
  153. Chia Yee Ooi and Hideo Fujiwara,"A New Scan Design Technique Based on Pre-Synthesis Thru Functions," 15th IEEE Asian Test Symposium (ATS'06), pp. 163-168, November 2006. [📄PDF]
  154. Masato Nakazato, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara, "Design for Testability of Software-Based Self-Test for Processors," 15th IEEE Asian Test Symposium (ATS'06), pp. 375-380, November 2006. [📄PDF]
  155. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, and Hideo Fujiwara,"Diagnosing at-speed scan BIST circuits using a low speed and low memory tester," 15th IEEE Asian Test Symposium (ATS'06), pp. 409-414, November 2006.  [📄PDF]
  156. Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Jiaguang Sun, and Hideo Fujiwara,"Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Architecture," 15th IEEE Asian Test Symposium (ATS'06), pp. 299-304, November 2006. [📄PDF]
  157. Ilia Polian, Bernd Becker, Masato Nakazato, Satoshi Ohtake, and Hideo Fujiwara,"Low-Cost Hardening of Image Processing Applications Against Software Errors," 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), pp. 274-279, October 2006. [📄PDF]
  158. Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, and Hideo Fujiwara, "Designing Power-Aware Wrapper for Multi-Clock Domain Cores Using Clock Domain Partitioning," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp. 43-48, November, 2006. [📄PDF]
  159. Hiroyuki Iwata, Tomokazu Yoneda, and Hideo Fujiwara, "A New Non-Scan DFT Method Based on the Time Expansion Model for RTL Controller-Datapath Circuits," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp. 7-12, November, 2006.  [📄PDF]
  160. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara, "An Optimal Test Bus Design for Transparency-Based SoC Test," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp. 21-26, November, 2006.  [📄PDF]
  161. Zhiqiang You, Michiko Inoue, and Hideo Fujiwara, "Extended Compatibilities for Scan Tree Construction," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp. 75-80, November, 2006.  [📄PDF]
  162. Toshinori Hosokawa, Ryoichi Inoue, and Hideo Fujiwara, "Fault Dependent/Independent Test Generation Methods for State Observable FSMs," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp. 13-18, November, 2006. [📄PDF]
  163. Danella Zhao, Unni Chandran, and Hideo Fujiwara, "Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores," Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07), pp. 714-719, January, 2007. [📄PDF]
  164. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, and Hideo Fujiwara, "Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses," Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07), pp. 720-725, January, 2007. [📄PDF]
  165. Tomokazu Yoneda, Masahiro Imanishi and Hideo Fujiwara, "An soc test scheduling algorithm using reconfigurable union wrappers," Design, Automation and Test in Europe (DATE'07), pp. 231-236, April 2007. [📄PDF]
  166. Thomas Ediosn Yu, Tomokazu Yoneda, Danella Zhao, and Hideo Fujiwara, "Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints," IEEE 25th VLSI Test Symposium (VTS'07), pp. 369-379, May, 2007. [📄PDF]
  167. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara, "TAM Design and Optimization for Transparency-based SoC Test," IEEE 25th VLSI Test Symposium (VTS'07), pp. 381-386, May, 2007. [📄PDF]
  168. Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara, "Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints," Proc. 12th IEEE European Test Symposium (ETS'07), pp. 35-40, May, 2007. [📄PDF]
  169. Satoshi Ohtake, Kosuke Yabuki, and Hideo Fujiwara, "Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure," Informal Digest of Papers, 12th IEEE European Test Symposium (ETS'07), pp. 131-136, May, 2007. [📄PDF]
  170. Danella Zhao, Ronghua Huang, Tomokazu Yoneda, and Hideo Fujiwara, "Power-Aware Multi-frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing," 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp.2942-2945, May, 2007. [📄PDF]
  171. Hiroyuki Iwata, Tomokazu Yoneda, and Hideo Fujiwara, "A DFT Method for the Time Expansion Model at the Register Transfer Level", 44th Design Automation Conference (DAC'07), pp. 682-687, June, 2007. [📄PDF]
  172. Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, and Hideo Fujiwara, "Thermal-safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip," IEEE 16th Asian Test Symposium (ATS'07), pp.187-192, October, 2007. [📄PDF]
  173. Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara, "Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing," IEEE 16th Asian Test Symposium (ATS'07), pp.459-462, October, 2007. [📄PDF]
  174. Yuki Yoshikawa, Satoshi Ohtake, and Hideo Fujiwara, "False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults ," IEEE 16th Asian Test Symposium (ATS'07), pp.65-68, October, 2007. [📄PDF]
  175. Tomokazu Yoneda, Yuusuke Fukuda, and Hideo Fujiwara, "Test Scheduling for Memory Cores with Built-In Self-Repair ," IEEE 16th Asian Test Symposium (ATS'07), pp.199-204, October, 2007. [📄PDF]
  176. Toshinori Hosokawa, Ryoichi Inoue, and Hideo Fujiwara, "Fault-dependent/independent Test Generation Methods for State Observable FSMs ," IEEE 16th Asian Test Symposium (ATS'07), pp.275-278, October, 2007. [📄PDF]
  177. Danella Zhao, Ronghua Huang, and Hideo Fujiwara, "Power-Conscious Multi-Frequency Modular Testing of SoCs with Dynamic Reconfiguration of Multi-Port ATE," IEEE 16th Asian Test Symposium (ATS'07), pp.107-110, October, 2007. [📄PDF]
  178. Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, and Hideo Fujiwara, "Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware ," IEEE 16th Asian Test Symposium (ATS'07), pp.329-334, October, 2007. [📄PDF]
  179. Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "RTL don’t care path identification and synthesis for transforming don’t care paths into false paths," Digest of Papers IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), pp. 9-15, October 2007.  <IEEE WRTLT'07 Best Paper Award>  [📄PDF]
  180. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara, "An Extended Class of Acyclically Testable Circuits," Digest of Papers IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), pp. 17-22, October 2007.  [📄PDF]
  181. Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara, "A Test Generation Method for State Observable FSMs to Increase Defect Coverage under the Test Length Constraint," Digest of Papers IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), pp. 79-86, October 2007. [📄PDF]
  182. Dong Xiang, Yang Zhao, Kaiwei Li, and Hideo Fujiwara, "Fast and effective fault simulation for path delay faults based on selected testable paths", 2007 IEEE International Test Conference, pp. 1-10, Oct., 2007. [📄PDF]
  183. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara,"Efficient path delay test generation based on stuck-at test generation using checker circuitry," IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), pp. 418-423, Nov. 2007. [📄PDF]
  184. Yu Hu, Xiang Fu, Xiaoxin Fan, and Hideo Fujiwara,"Localized Random Access Scan: Towards Low Area and Routing Overhead," 13th Asia and South Pacific Design Automation Conference (ASP-DAC'08), pp. 565-570, Jan. 2008. [📄PDF]
  185. Tomokazu Yoneda and Hideo Fujiwara,"Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects," Design, Automation and Test in Europe (DATE'08), pp. 1366-1369, March, 2008. [📄PDF]
  186. Elena Hammari, Michiko Inoue, Einar J. Aas, Hideo Fujiwara,"Bidirectional Delay Test of FPGA Routing Networks," Informal Digest of Papers, 13th IEEE European Test Symposium (ETS'08), May, 2008. [📄PDF]
  187. Jaan Raik, Hideo Fujiwara, Raimund Ubar, and Anna Krivenko, "Untestable Fault Identification in Sequential Circuits Using Model-Checking ," Proc. of IEEE the 17th Asian Test Symposium (ATS'08), pp. 21-26, Nov. 2008. [📄PDF]
  188. Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara, "A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint ," Proc. of IEEE the 17th Asian Test Symposium (ATS'08), pp. 27-34, Nov. 2008. [📄PDF]
  189. Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, and Hideo Fujiwara,"Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths," Proc. of IEEE the 17th Asian Test Symposium (ATS'08), pp. 125-130, Nov. 2008. [📄PDF]
  190. Takashi Yoshida, Tomokazu Yoneda and Hideo Fujiwara, "A reconfigurable wrapper design for multi-clock domain cores," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp. 13-18, Nov. 2008.  [📄PDF]
  191. Hideo Fujiwara, Chia Yee Ooi and Yuki Shimizu, "Enhancement of test environment generation for assignment decision diagrams," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.45-50, Nov. 2008.  <IEEE WRTLT'08 Best Paper Award> [📄PDF]
  192. Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri and Hideo Fujiwara, "A new class of easily testable assignment decision diagram," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp. 51-56, Nov. 2008. [📄PDF]
  193. Jaan Raik, Hideo Fujiwara, and Anna Krivenko, "RT-level identification of potentially testable initialization faults," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.57-62, Nov. 2008. [📄PDF]
  194. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara, "An approach to RTL-GL path mapping based on functional equivalence," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.63-68, Nov. 2008. [📄PDF]
  195. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara," Fast False Path Identification Based on Functional Unsensitizability Using RTL Information,"14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp.660-665, Jan. 2009. [📄PDF]
  196. Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara," Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints,"14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp.793-798, Jan. 2009. [📄PDF]
  197. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara, "Unsensitizable Path Identification at RTL Using High-Level Synthesis Information," 16th IEEE International Test Synthesis Workshop (ITSW 2009), Mar. 2009.  [📄PDF]
  198. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara," A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification,"IEEE VTS'09 (27th VLSI Test Symposium), pp.71-76, May 2009. [📄PDF]
  199. Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara," Partial Scan Approach for Secret Information Protection," 2009 IEEE European Test Symposium, pp.143 -148, May 2009.  [📄PDF]
  200. Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara," Test Generation and DFT Based on Partial Thru Testability," 2009 IEEE European Test Symposium, poster session, May 2009.  [📄PDF]
  201. Michiko Inoue, Tsuyoshi Suzuki and Hideo Fujiwara, "Acceleration by Contention for Shared Memory Mutual Exclusion Algorithm", Proc. 23rd International Symposium on Distributed Computing (DISC 09), pp. 172-173, Sept. 2009.
  202. Yasuo Sato, Seiji Kajihara, Yukiya Mimura, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A Circuit Failure Prediction Mechanism (DART) for High Field Reliability, Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp. 581- 584, Oct. 2009. [📄PDF]
  203. Marie Engelene J. Obien and Hideo Fujiwara, "F-Scan: An Approach to Functional RTL Scan for Assignment Decision Diagrams", Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp. 589- 592, Oct. 2009. [📄PDF]
  204. Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, and Hideo Fujiwara, "A Response Compactor for Extended Compatibility Scan Tree Construction", Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp. 609- 612, Oct. 2009. [📄PDF]
  205. Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara,"RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences," IEEE International High Level Design Validation and Test Workshop 2009 (IEEE HLDVT 2009), pp. 160-165, Nov. 2009. [📄PDF]
  206. Marie E. J. Obien and Hideo Fujiwara, "A DFT Method for Functional Scan at RTL," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp. 6-15, Nov. 2009.  <IEEE WRTLT'09 Best Paper Award> [📄PDF]
  207. Michiko Inoue, Satoshi Ohtake, Yu-ichi Uemoto and Hideo Fujiwara, "Path-based Resource Binding to Reduce Delay Fault Test Cost," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp. 29-32, Nov. 2009.  [📄PDF]
  208. Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Hideo Fujiwara, "Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp. 43-48, Nov. 2009. [📄PDF]
  209. Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara, "Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp. 16-22, Nov. 2009. [📄PDF]
  210. Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, and Adit D. Singh, "On Minimization of Test Application Time for RAS," 23rd Internaional Conference on VLSI Design, pp. 293-398, Jan. 2010. [📄PDF]
  211. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, and Hideo Fujiwara, "Optimizing Delay Test Quality with a Limited Size of Test Set," First IEEE International Workshop on Reliability Aware System Design and Test (RASDAT 2010), pp. 46-51, Jan. 2010. [📄PDF]
  212. Hideo Fujiwara and Marie E. J. Obien,"Secure and Testable Scan Design Using Extended de Bruijn Graphs," 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp.413-418, Jan. 2010. [📄PDF]
  213. Hiroshi Iwata, Satoshi Ohtake, and Hideo Fujiwara, "Enabling False Path Identification from RTL for Reducing Design and Test Futileness," The 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), pp. 20-25, Jan. 2010. [📄PDF]
  214. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, and Hideo Fujiwara, "A Method of Unsensitizable Path Identification using High Level Design Information," 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2010), March 2010.  [📄PDF]
  215. Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, and Hideo Tamamoto, "SREEP: Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design," 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2010), pp. 193-196, April 2010. [📄PDF]
  216. Satoshi Ohtake, Hiroshi Iwata, and Hideo Fujiwara, "A Synthesis Method to Propagate False Path Information from RTL to Gate Level," 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), pp. 197-200, April 2010.  [📄PDF]
  217. Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, and Hideo Fujiwara, "Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing," 28th IEEE VLSI Test Symposium (VTS 2010), pp.188-193, April 2010. [📄PDF]
  218. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Scan Cells Reordering to Minimize Peak Power during Test Cycle: A Graph Theoretic Approach," 2010 IEEE European Test Symposium, May 2010. [📄PDF]
  219. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, and Hideo Fujiwara, "Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set," 2010 IEEE European Test Symposium, May 2010. [📄PDF]
  220. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Graph Theoretical Approach for Scan Cell Reordering to Minimize Peak Shift Power," ACM Great Lake Symposium on VLSI (GLSVLSI 2010), pp. 73-78, May 2010. [📄PDF]
  221. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, and Hideo Fujiwara, "Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction," IEEE International On-Line Testing Symposium (IOLTS'10), pp. 21-26, July 2010. [📄PDF]
  222. Marie Engelene Jimenez Obien, Satoshi Ohtake, and Hideo Fujiwara, "Delay Fault ATPG for F-Scannable RTL Circuits," IEEE Int. Symp. on Communications and Information Technologies (ISCIT'10), pp. 717-722, Oct. 2010. [📄PDF]
  223. Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara, "Constrained ATPG for Functional RTL Circuits Using F-Scan," 2010 IEEE International Test Conference, Paper 21.1, Nov. 2010.  [📄PDF]
  224. Alodeep Sanyal, Krishnendu Chakrabarty, Mahmt Yilmaz, and Hideo Fujiwara, "RT-Level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage," 2010 IEEE International Test Conference, Paper 21.2, Nov. 2010.  [📄PDF]
  225. Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara, "Bipartite Full Scan Design:  A DFT Method for Asynchronous Circuits," Proc. of IEEE the 19th Asian Test Symposium (ATS'10), pp. 206 - 211, Dec. 2010. [📄PDF]
  226. Tomokazu Yoneda, Michiko Inoue, Akira Taketani, and Hideo Fujiwara, "Seed Ordering and Selection for High Quality Delay Test," Proc. of IEEE the 19th Asian Test Symposium (ATS'10), pp. 313-318, Dec. 2010. [📄PDF]
  227. Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, and Hideo Fujiwara, "Capture in Turn Scan for Reduction of Test Date Volume, Test Application Time and Test Power," Proc. of IEEE the 19th Asian Test Symposium (ATS'10), pp. 371-374, Dec. 2010. [📄PDF]
  228. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "SREEP-2:  SR-Equivalent Generator for Secure and Testable Scan Design," 11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp. 7-12, Dec. 2010.  [📄PDF]
  229. Chia Yee Ooi and Hideo Fujiwara, "Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults," 11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp. 139-144, Dec. 2010. [📄PDF]
  230. Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar, and Taavi Viilukas, "An Approach for Verification Assertions Reuse in RTL Test Pattern Generation," 11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp. 107-110, Dec. 2010. [📄PDF]
  231. Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda, and Hideo Fujiwara, "RedSOCs-3D:  Thermal-safe Test Scheduling for 3D-Stacked SoC," 2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Dec. 2010.  [📄PDF]
  232. Hideo Fujiwara, Katsuya Fujiwara, and Hideo Tamamoto, "Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack," 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.818-823, Jan. 2011.  [📄PDF]
  233. Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Hideo Fujiwara, and Raimund Ubar, "Constrained-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits," 2011 IEEE European Test Symposium, May 2011.  [📄PDF]
  234. Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara, "F-Scan Test Generation Model for Delay Fault Testing at RTL using Standard Full Scan ATPG," 2011 IEEE European Test Symposium, May 2011.  [📄PDF]
  235. Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, and Hideo Fujiwara, "Temperature-Variation-Aware Test Pattern Optimization," 2011 IEEE European Test Symposium, May 2011.  [📄PDF]
  236. Tomokazu Yoneda, Keigo Hori, Michiko Inoue, and Hideo Fujiwara, "Faster-Than-At-Speed Test for Increased Test Quality and In-Field Reliability," 2011 IEEE International Test Conference, Paper 2.2, Sept. 2011.  [📄PDF]
  237. Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "SR-Quasi-Equivalents: Yet Another Approach to Secure and Testable Scan Design," 12th IEEE Workshop on RTL and High Level Testing (WRTLT'11), pp. 77-82, Nov. 2011.  [📄PDF]
  238. Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'Ameri, and Hideo Fujiwara, "Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram," 12th IEEE Workshop on RTL and High Level Testing (WRTLT'11), pp. 9-15, Nov. 2011.   <IEEE WRTLT'11 Best Paper Award> [📄PDF]
  239. Hiroaki Fujiwara, Toshinori Hosokawa, Ryoichi Inoue, and Hideo Fujiwara, "A Binding Method for Hierarchical Testing Using Results of Test Environment Generation," 12th IEEE Workshop on RTL and High Level Testing (WRTLT'11), pp. 16-22, Nov. 2011. [📄PDF]
  240. Yinghua Min and Hideo Fujiwara, "The Past and Future of WRTLT," 13th IEEE Workshop on RTL and High Level Testing (WRTLT'12), pp. II.2.1-II.2.4, Nov. 2012. [📄PDF]
  241. Katsuya Fujiwara and Hideo Fujiwara, "WAGSR: Web Application for Generalized Feed Forward Shift Registers," 13th IEEE Workshop on RTL and High Level Testing (WRTLT'12), pp.1.2.1-1.2.7, Nov. 2012.  [📄PDF]
  242. Dong Xiang, Gang Liu, Krishnendu Chakrabarty, and Hideo Fujiwara, "Thermal-Aware Test Scheduling for NOC-Based 3D Integrated Circuits," 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 99-104, Oct. 2013.  [📄PDF]
  243. Jun Nishimaki, Toshinori Hosokawa, and Hideo Fujiwara, "Functional Unit and Register Binding Methods for Hierarchical Testability," 14th IEEE Workshop on RTL and High Level Testing (WRTLT'13),  Nov. 2013.  [📄PDF]
  244. Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa, and Hideo Fujiwara, "A Controller Augmentation Method to Generate Easily Testable Functional k-Time Expansion Models for Data Path Circuits," 14th IEEE Workshop on RTL and High Level Testing (WRTLT'13), Nov. 2013.  [📄PDF]
  245. Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, "A Scheduling Method for Hierarchical Testability Using Results of Test Environment Generation," 15th IEEE Workshop on RTL and High Level Testing (WRTLT'14), Nov. 2014. <IEEE WRTLT'14 Best Paper Award> [📄PDF]
  246. Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, “A Binding Method for Hierarchical Testability Using Results of Test Environment Generation,” 2nd Workshop on Design Automation for Understanding Hardware Designs (DUHDe2015), March 2015. [📄PDF]
  247. Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, "A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation," IEEE the 24th Asian Test Symposium (ATS'15), pp. 37-42, Nov. 2015. [📄PDF]
  248. Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, "A Scheduling Method for Hierarchical Testability Based on Test Environment Generation Results," 21st IEEE European Test Symposium (ETS'16), pp. 5-6, May 2016. [📄PDF]
  249. Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara, " A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs," IEEE International Test Conference 2016 (ITC'16), Nov. 15-17, 2016. [📄PDF]
  250. Hiroshi Yamazaki, Toshinori Hosokawa and Hideo Fujiwara, "Strongly Secure Scan Design Using Extended Shift Registers," 17th IEEE Workshop on RTL and High Level Testing (WRTLT'16), Nov. 2016. [📄PDF]
  251. Mamoru Sato, Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, "A Binding Method to Generate Easily Testable Functional Time Expansion Models," 17th IEEE Workshop on RTL and High Level Testing (WRTLT'16), Nov. 2016. [📄PDF]