The complexity of leading-edge VLSI products (as defined by the number of transistors on a chip) increases exponentially with time because of the underlying semicondutor technology and historical trends. It has become possible to design entire systems onto a single chip, commonly known as System-on-Chip (SoC). The difficulty of the design and test tasks for such SoCs is currently being accelerated and limits our ability to fully utilize new fabrication techniques, a problem known as the design and test crisis. To overcome this crisis, a breakthrough in design and test technologies will be needed. Core-based system-on-chip design strategies with automated high-level synthesis for cores is a potential means of overcoming the VLSI design complexities. High-level testability designs are essential in order to minimize test complexity without affecting area or performance. Automated generation of optimized test architecture for core-based SoCs is also an essential means of reducing the time-to-market and design and test cost for VLSI products. We are currently focusing on research into a high-level synthesis of high performance and high testability VLSI circuits as well as designs for testability at the RT (register-transfer) level and logic level, based on not only external test but also BIST (built-in self-test). We are also focusing on research of a global design for test methodology and optimization technique for testing core-based SoCs. Other ongoing projects on VLSI design and testing include theoretical research on sequential circuits with combinational test generation complexity, super-efficient and robust test generation algorithms for ultra-large-scale combinational circuits, and parallel processing for test generation.

Logic Design Theory / Digital Systems Design and Test / VLSI CAD

This area includes research into design and test for systems-on-a-chip, high-level synthesis for testability, logic synthesis for testability, design for testability, test synthesis, test generation, fault simulation, parallel processing for CAD, etc.

Highly Reliable Design / Fault Tolerant Computing

Includes highly reliable design for VLSIs, built in self test for VLSIs, high reliable multi processor systems, fault tolerant systems, etc.

Hardware/Software Co-Design

Includes CAD for H/S co-design, hardware algorithms, design and test of reconfigurable hardwares (FPGAs), etc.