Guest Editor, Special Issue on Verification, Test,
Diagnosis for VLSI Systems, IEICE Trans. on Information and Systems,
IEICE Japan, May 1992 - March 1995
Chair, Technical Group on Fault Tolerant Systems, IEICE Japan, May 1995 - May 1997
Guest Editor, Special Issue on Test Technology, IEICE Trans. (D-I) (in Japanese), IEICE Japan, Oct. 1995 - Dec. 1996
Member, Technical Group on Fault Tolerant Systems/Dependable Computing, IEICE Japan, May 1997 - May 2006
Associate Editor, IEEE Transactions on Computers, May 1998 - May 2002
Chair, IEEE ATS (Asian Test Symposium) Steering Committee, January 2001 - Dec. 2004
Chair, IEEE WRTLT (Workshop on RTL and High Level Testing) Steering Committee, Nov. 2003 - Dec. 2006
Board Member of IEEE Kansai Section (in Japan, Region 10), Jan. 2003 - Dec. 2008
Associate Editor, Journal of Electronic Testing:Theory and Applications, Kluwer Academic Publishers, Oct. 1989 - Dec. 2004
Associate Editor, Journal of Circuits, Systems and Computers, World Scientific, Dec. 1989 - Dec. 2004
Grants and Funding
Joint Research with the Private Sector
NTT Communication Science Laboratories "Research on Design Support Technology of Hardware/Software Co-Design" 1994 - 1995
Matsushita Electric Industrial Co. Ltd. "Research on RTL Design for Testability Technology" 1995 - 1996
Sharp Corporation "Research on Built-In Self-Test for Micro-Controllers" 1996 - 1997
STARC (Semiconductor Technology Academic Research Center)
"Research on High Level Synthesis of High Performance and High
Testability VLSI Circuits" 1997 - 2000
STARC (Semiconductor Technology Academic Research Center)
"Research on Instruction-level Self-test and Design-for-testability for
Processors" 2003 - 2005
STARC (Semiconductor Technology Academic Research Center)
"Research on test time and yield loss reduction through false path
indentification and its propagation from behavioral to structural
representations" 2006 - 2008
Commissioned Research
TAO (Telecommunications Advancement Organization of Japan)
"Research on High-Speed and High-Reliable Satellite Communication
Systems" 1996 - 1998
STARC (Semiconductor Technology Academic Research Center)
"Research and Development on V-Core Based Design for Testability
Technology" 2000 - 2002
Grant-in-Aid for Scientific Research
Grant-in-Aid for Encouragement of Young Scientists
Grant-in-Aid for Scientific Research (C) "Research on
Neural Networks for Test Generation of Large Scale Logic Circuits" 1991
- 1992
Grant-in-Aid for Scientific Research (C) "Research on
Parallel Processing for Test Generation of Large Scale Logic Circuits"
1993 - 1994
Grant-in-Aid for Scientific Research (B) "Research on Synthesis for Testability from Higher Level" 1997 - 2000
Grant-in-Aid for JSPS Fellows "VLSI Testing and Design for Testability" (1999 - 2001)
Grant-in-Aid for JSPS Fellows "Test Scheduling and Test Access Mechanism for System-on-Chip" (2001 - 2002)
Grant-in-Aid for Scientific Research (B) "Research on Test Architecture
and Design for Testability for System-on-a-Chip" (2003 - 2006)
Grant-in-Aid for Scientific Research (B) "Research on Testability and Security for Network-on-a-Chip" (2008 - 2010)
Grants and Endowments
Fujitsu Laboratories, Ltd. (? - 1994)
Hitachi, Ltd. (Hitachi Laboratories) (? - 1999)
STARC (Semiconductor Technology Academic Research Center) (1998 - 2000)
NEC Corporation (? - 2001)
Hitachi, Ltd. (Enterprise Server Division )(? - 2001)
Hitachi, Ltd. (Central Research Laboratory)(1999 - 2002)
Mitsubishi Electric Corp. (2001)
STARC (Semiconductor Technology Academic Research Center) (2002 - 2008)